Artificial intelligence has turned the entire memory and storage stack — HBM, DRAM, NAND and hard disk — into the scarcest resource in computing. Every wafer routed to AI memory, and every platter routed to a hyperscaler, is denied to the device in your hands.
A standing dashboard of the whole memory landscape, from the fastest HBM cube to the coldest nearline drive. Pricing, market share, the company roster and the signal feed pull current figures live through Claude with web search; everything renders from a compiled baseline first.
Four tiers, fastest and priciest at top to cheapest-per-terabyte at bottom. AI demand is straining every one of them at once — the first time the whole stack has gone tight together.
Pricing momentum is slowing, not reversing: the latest 3Q26 guide is DRAM +13–18% QoQ and NAND +10–15%. Samsung’s record Q2 preliminary profit and Micron’s larger U.S. buildout confirm that tightness still spans HBM, conventional DRAM, NAND and storage.
Every kind of memory and storage, what it physically is, how it works, and where it's used. The whole industry splits on one line: volatile memory that needs constant power to remember, and non-volatile storage that keeps data when the power is off. Speed and cost trade off against capacity all the way down.
Added to the field guide’s context: SPHBM4 is a newly standardized lower-cost packaging path that keeps HBM4-class stacks but narrows the external interface so systems can use organic substrates rather than large silicon interposers.
Holds data only while powered. It's fast and sits close to the processor, acting as the workspace a chip computes in. Cut the power and it forgets instantly. This is "memory" in the strict sense — SRAM and DRAM, including HBM.
Keeps data with the power off. It's slower but far cheaper per gigabyte and vastly higher capacity, so it stores everything persistently — the operating system, apps, files, models and archives. This is "storage."
The memory hierarchy above — tiny-and-instant at the top, vast-and-slow at the bottom — rhymes with how neuroscientists describe human memory: a fast, fragile "working" store for what you're thinking about right now, and slower, durable stores for what you've learned. The mapping below is a teaching aid, not a literal equivalence. It's genuinely useful for intuition, and genuinely misleading if taken too far — so the honest caveats follow right after.
Latencies and layer counts are representative orders of magnitude — exact figures vary by product, generation and process. "AI" tags mark tiers being reshaped directly by AI demand. The boundary between memory and storage is blurring: HBF, storage-class memory and CXL pooling all aim at the gap between fast-but-small DRAM and cheap-but-slow flash. The brain mapping is an educational analogy; neuroscience is still actively researching how human memory is encoded, consolidated and retrieved, and no current model treats the brain as a literal storage hierarchy.
The July evidence cuts both ways: Samsung estimated ₩89.4T of Q2 operating profit, while memory equities sold off on fears that AI capex returns will moderate. The structural shortage remains, but investor expectations are now a larger risk than near-term earnings.
Memory has always been brutally cyclical. The 2026 shortage breaks the pattern because it is demand-driven, not supply-driven — and it spans the entire stack at once. The 2021 crunch came from shuttered fabs; it healed when factories reopened.
This time the constraint is AI itself. Training and inference are bandwidth-bound, so GPU racks swallow HBM; the data they train on needs enterprise SSDs; the exhaust — checkpoints, logs, generated media — lands on nearline HDD. Makers pour capacity into the high-margin top of the stack, starving everything below.
Relief in volume isn't expected until late 2027–2028. Until then hyperscalers pre-pay to lock allocation. Hard-drive makers have sold out 2026 with agreements stretching to 2028; the three memory makers have added roughly $900 billion in combined market value since September 2025. Crucially, the makers are choosing not to flood the market: Samsung and SK hynix can fulfill only ~70% of DRAM orders yet are deliberately restraining capex to "minimize the risk of oversupply" — the discipline that could make this cycle outlast prior boom-busts (or, cynically, exactly what every supplier says before a glut).
HBM's stacked construction is far more wafer-intensive than ordinary memory — one bit of HBM forgoes ~three bits of standard DRAM. HBM alone now absorbs an estimated 23% of all DRAM wafers, draining the commodity pool that feeds phones, PCs and SSDs.
The investor's section. Memory is the most violently cyclical corner of tech — so the questions that matter aren't "is AI big?" but where are we in the cycle, what sustains it, and what breaks the thesis? This pulls together the leading indicators: the bit supply-demand gap, capex (the supply pipeline), valuation in cycle context, and an explicit bear case with the signals that would flip each risk.
Cycle read remains boom / late-6th inning. The price level is still rising, but the second derivative has weakened and Korea’s benchmark briefly entered a 20% drawdown from its June peak—classic evidence that the equity cycle can turn before the physical-memory cycle.
Memory cycles run trough → recovery → boom → peak → correction. Every prior cycle has reverted: in the 2017–18 DRAM supercycle, supply tightened, margins crossed 50%, analysts declared the cycle "structurally different" — then supply caught up and margins fell toward zero within two years.
This cycle has a more credible structural case (AI demand + the HBM wafer tax constraining supply). But the mechanism that ends memory cycles hasn't changed: high margins attract capacity, capacity arrives in 12–18 months, and the gap closes.
When annual bit-demand growth runs above bit-supply growth, prices rise and the cycle is bullish. When supply growth crosses above demand, the cycle turns. Right now demand leads on both DRAM and NAND — but the gap is the thing to watch, not the price.
The bull case rests on supply being unable to respond. Here's the evidence: even with record profits, the big three are spending cautiously — and Micron's new capacity (Idaho) doesn't come online until 2027. Capex up only ~14% against demand up ~20%+ is why the shortage persists.
Modeled quarterly DRAM bit balance in billion gigabytes (GB): positive bars = supply surplus, negative = deficit. Real high-confidence anchors (TrendForce, Micron earnings) define the shape through 2026; everything beyond is an explicit modeled scenario, not a forecast — interest rates and AI demand 10 years out aren't really knowable. The whole point of plotting it is to make the assumptions inspectable.
Assumptions checked against the newest prints (Jul 12 2026): the deficit shape through 2026 still matches the data — but the rate story has a fresh anchor: TrendForce’s 3Q26 call has conventional DRAM contract prices decelerating to +13–18% QoQ (from ~+90s%) as consumer buyers hit an affordability ceiling (§03, kill-switch #1) — consistent with a deficit that is peaking, not widening. On the supply side, kill-switch #2 is ARMED for CY2028 (§02·D): 2026–27 capacity announcements land as the bear case’s 2028 flood if they all ship. Two structural offsets the model carries via the HBM wafer tax: Micron’s take-or-pay SCAs now lock ~20% of DRAM and ~30% of NAND through 2030 (§06·F·M), and HBM3E+HBM4 are booked through 2027 into 2028 (§10 feed, Jun 24). Modeled bars beyond 2026 were not rewritten on one quarter’s print — the scenario spread (bull/base/bear) is the honest container for that uncertainty; watch the Jul 23 Samsung/SK capex commentary (§02·E) for the next assumption test.
Anchors (high-confidence quarters): 2022Q1–Q4 surplus from TrendForce's "DRAM 2022 oversupply, bit supply +18.6% vs demand +17.1%"; 2023 trough from the documented ~30% memory revenue collapse; 2024 recovery from TrendForce; 2025 transition to deficit from rising contract prices; 2026 record deficit from Micron's December 2025 disclosure that "supply will remain substantially short of demand" and the industry can meet only half to two-thirds of demand. Modeled beyond 2026Q4 using: bit-demand CAGR (base 18%, bull 22%, bear 14%); supply growth lagged ~6 quarters behind capex (Micron Idaho online 2027; second fab 2028); and historical cycle behavior (memory always reverts — bear case = 2017-18 precedent applied). Quarters are interpolated within annual anchors using observed seasonality. This is a model, not a prediction. The further right you look, the wider the error band.
Every thesis needs its disconfirming evidence. These are the real risks, ranked by severity, each paired with the specific signal that would tell you it's materializing.
The crux of the bull thesis isn't just demand — it's that the three makers are deliberately not flooding the market. They're fulfilling only ~70% of orders yet restraining capex to protect pricing, and the new fabs that would break the shortage don't come online until 2027–28. This is the structural reason prices may stay high longer than a normal cycle — and, read cynically, also the setup for an eventual glut. The same fact supports both the bull and bear case.
Bit-growth, capex and TAM figures: TrendForce, Micron earnings, IDC, Counterpoint (2025–26 actuals; 2027–28 forecast). Supply-discipline figures: Samsung & SK hynix Q1 2026 earnings calls (~70% DRAM fulfillment, ~30%-of-sales capex, record profits), TrendForce (demand +35% vs supply +23% in 2026), DCD / Tom's Hardware (fab timing: SK M15X output 2H 2026→ramp 2027, Samsung P5 ~2028, Micron Japan H2-2028). The 2017–18 precedent: SK Hynix/Micron margins fell from 50%+ toward zero within ~2 years as supply caught up. Micron's own 10-K notes DRAM ASPs have swung between +40% and −40% year-over-year in the past five years. P/B ranges are approximate cycle bands. Cycle-phase placement is a judgment call, not a precise measurement. Everything here is analysis, not investment advice — and the bear case is as evidence-based as the bull case deliberately.
A 9-inning baseball read on the memory supercycle — an intuitive translation of the cycle-position analysis above. The 9 innings run from the 2023 trough (the bottom of the order) to the eventual peak and turn. Reviewing every signal in this dashboard — the bit-gap, prices, inventory, capex discipline, and the projected supply wave — here's the call.
The call moves from “middle of the 6th” to late 6th: earnings and shortages still argue against the 7th-inning peak, while price deceleration, crowded positioning and the Korean selloff argue the easy multiple-expansion innings are over.
Prices have already spiked hard (DRAM up ~9× off the 2023 trough), so the early innings are clearly behind us. But the shortage is still structural: demand outruns supply, inventories are at record lows, capex is still disciplined, and no meaningful new fab capacity arrives until 2027. The peak (earnings top, projected Q4'26–Q2'27) is the 7th-inning stretch — still 2–4 quarters away — and the supply wave that ends the game is an 8th/9th-inning event in 2027–28.
Mid–late 2025: the AI shortage bit hard, contract prices spiked, and Korea's export data hit records (+60% MoM in Jan 2026). The move that made the headlines.
2026 now: demand still > supply, inventories record-low, capex still restrained so supply can't yet respond. Prices climbing but the rate of ascent is what to watch.
Late 2026–2027: earnings peak (Q4'26–Q2'27), valuations stretched, sentiment euphoric. The 7th-inning stretch — the top comes into view but isn't here yet.
If AI demand keeps compounding and HBM's 3:1 wafer tax keeps commodity DRAM structurally starved, this upcycle could run longer than a normal memory cycle. The new supply-discipline evidence cuts this way: Samsung/SK hynix are restraining expansion (only ~70% order fulfillment), meaningful new volume doesn't land until 2027–28 (SK M15X ramps 2027, Samsung P5 ~2028, Micron Japan H2-2028), and research firms now say "no scenario where prices correct in 2H 2027." The game stretches — the peak slips toward 2028.
A demand air-pocket — an AI capex pause, or a double-ordering unwind — could end the game abruptly, jumping straight to the 9th. Memory's history is full of games called on account of rain: in 2017–18, margins went from 50%+ to near zero in two years once the mood turned. The disciplined-supply story is itself the risk: every maker is also quietly adding capacity (Samsung P5, SK M15X/Yongin, Micron Japan/Virginia), and "minimize oversupply" is precisely what suppliers say right before a glut. Wildcard: helium supply (critical to fabs) is exposed to the Middle East conflict.
This is an analogy, not a measurement — memory cycles don't have fixed innings, and the inning number is a judgment that translates the cycle-position analysis (§02·B) into an intuitive frame. It rests on the same signals shown throughout this dashboard: the bit-gap (demand still leads), prices (already spiked), inventory (record-low), capex (disciplined, supply can't respond until 2027), and the modeled supply/demand balance (crosses over ~2027). The honest range is the 5th–7th. The game can go to extra innings or be called early — and the further into the late innings you think we are, the more the risk register (§02·B) matters. Not investment advice.
The bear case, concentrated: six falsification criteria that would break or bend the supercycle thesis, each with a status as of Jul 12 2026 and the specific evidence that flips it. Statuses are dated judgments, not predictions — the whole point is that they're checkable. One is already tripped.
As of Jul 12: KS#1 pricing-power inflection remains tripped early; the leveraged-positioning/volatility switch is now more active after the KOSPI selloff and regulatory review. Supply relief and hyperscaler demand cancellation are not yet tripped.
Method. Statuses are dated editorial judgments (Jul 12 2026) applied to sourced readings: Micron FQ3 call and prepared remarks (moderation guidance, SCA ceilings, inventory days, price moves); §02·B fab timeline (Micron CY2028 greenfield, SK M15X 2027, Samsung P5 ~2028); TrendForce CoWoS reporting (Jun 2026) and TSMC expansion disclosures; Samsung 2026 HBM contract reporting; §09 for China positioning; 2018/2021 cycle references are approximate historical figures, labeled as such. This section exists because of the honesty contract: a thesis that can't name what would falsify it isn't a thesis. Not investment advice.
Every dated event on the board for the next six months, in one place — pulled from the "what to watch" threads scattered across the dashboard. Each row says which sections it feeds and which kill-switch (§02·D) it tests, so the calendar reads as a falsification schedule, not a hype reel. Dates marked ~ are approximate windows from company IR history.
Samsung preliminary earnings and the SK hynix Nasdaq listing are now completed events. The next hard checks are Korea’s Jul 1–20 export flash, Tesla and hyperscaler earnings, and Samsung/SK hynix full-quarter detail.
| Date | Event | Feeds | Tests |
|---|---|---|---|
| Jul 7 · done | Samsung Q2 preliminary: ₩89.4T operating profit; ₩171T revenue | §02–§05 | KS#1: record earnings, slower price-growth concern |
| Jul 10 · done | SK hynix ADR debuted on Nasdaq; $26.5B sale, 14% opening jump | §04 · §04·F | KS#6: access/leverage plumbing expanded |
| Jul 15 | CXMT Shanghai IPO book-building begins | §09 · §06·E | China supply funding / commodity-share risk |
| Jul 21 | Korea customs 1–20 Jul flash exports | §03·B | KS#1: does June price/kg dip extend? |
| Jul 22 | Tesla Q2 financials; Alphabet Q2 | §07·B·T · §06·F·B | edge margin + hyperscaler capex/RPO |
| Jul 23–30 | SK hynix and Samsung full Q2 details | §04 · §05 · §06·E | HBM mix, capex and conventional-memory pricing |
| ~Aug 1 | Korea July full-month export price/kg | §03·B | second monthly decline would strengthen inflection case |
| ~Aug 26 | NVIDIA FQ2 | §06 · §06·C | accelerator pull-through and HBM allocation |
| ~Sep 9–11 | Oracle FQ1 RPO update | §06·F·B | KS#5: backlog trajectory |
| ~Sep 22–24 | Micron FQ4 + FY2026 results | most sections | KS#1: guided moderation versus realized pricing |
| Dec 9 | Micron CHIPS milestone | §06·F·M | U.S. capacity execution |
Provenance. Compiled Jul 12 2026 from company IR calendars and completed-event results and the dated "what to watch" notes already cited in the linked sections; approximate windows marked ~. Scheduled dates shift — each row states what the event would corroborate or falsify rather than predicting its outcome. Not investment advice.
A decade of contract prices in one chart — five years of history, today, and five years of consensus forecasts. The 2021 peak gave way to the brutal 2022–23 crash (DRAM and NAND each lost ~30–40%), a brief 2025 soft patch, then the AI ignition that became the supercycle. Forward of Q1 2026 (dashed), the lines plot the path most analysts now see: another ~10% climb into 2H26, a plateau through 2027, then a gradual softening as new fab capacity comes online in 2028–2030.
The baseline now uses the 3Q26 +13–18% DRAM / +10–15% NAND guide in the headline and marks Q2 2026 as historical. Samsung’s Q2 disclosure also cited more moderate DRAM price growth than some investors expected.
HBM is priced per stack — each generation a steep premium (market estimates, 2026):
South Korea exports roughly 70% of the world's DRAM (Samsung + SK Hynix), so its monthly customs export-price data is one of the cleanest real-time reads on the memory market — published faster than contract-price surveys. This tracks the average DRAM export unit price, monthly, over the past three years. It attempts to refresh live; opened as a plain file it shows the compiled series (through the latest reported month).
June remains the latest complete Korean customs month. July 1–20 flash data is the next high-frequency checkpoint; the dashboard retains June’s first MoM decline in nine months rather than fabricating a July point.
Hard anchors (real customs/government data): Jan 2026 DRAM export price/kg = $28,057, +133.6% YoY, ≈+60% MoM, monthly export value a record ~$8.67B (Hankyung Aicel / Korea Customs); Mar 2026 semiconductor exports $32.83B, +151.4% YoY — the first month ever above $30B (MOTIE); Q1 2026 DRAM exports $35.79B (+249.1% YoY) and NAND $5.39B (+377.5%) on the revised MTI codes, while export tonnage fell ~12% YoY — 2.7× the value on less weight, the HBM-mix signature (MOTIE, KITA, Korea Herald, AJU); May 2026 DRAM exports $18.6B, +369.8% YoY; semis $37.16B (+169.4%), 42.3% of all exports (KITA, TradingEconomics); Jun 2026 DRAM export price/kg ≈$60,000, down ~$1,000 MoM — the first monthly decline in nine months, with semiconductor exports $44.82B (43.8% share) as total Korean exports crossed $100B for the first time (Seoul Economic Daily / MOTIE, Jul 1). Revision note: the Feb–May 2026 interpolated points were re-fit upward when the May/Jun $/kg prints arrived — the earlier path (built before those prints) understated the spring surge by ~40%; 2025 quarterly DRAM fixed price $1.35 → $2.12 → $5.30 → $8.13 (NABO, Korea Customs & Trade Development Institute); Dec 2024 chip exports +31.5% on HBM/DDR5 strength despite general-memory price softness (MOTIE); 2023 documented downcycle — general-purpose memory prices fell sharply (the ~30% chip-revenue collapse). Months between anchors are interpolated to fit the documented quarterly averages and reported MoM/YoY moves. This is an indexed reconstruction calibrated to public Korean trade data, not a verbatim monthly customs series (Korea publishes export value and weight monthly; a clean per-bit price index requires combining them). Real-time updates depend on running inside Claude; the baseline is current to the latest reported month. Sources: Korea Customs Service, MOTIE, Bank of Korea, NABO, KED Global, Hankyung Aicel. Not investment advice.
The longest lens on the board. For a quarter century, DRAM had one economic constant: $/GB fell relentlessly — from roughly ~$180/GB in 2001 (DDR1) to a glut-trough near ~$1.60/GB in 2023, a ~110× decline, punctuated only by cyclical bumps (2017–18’s supercycle among them) that always mean-reverted within ~2 years. 2024→2026 is different in kind: ~6× off the trough to ~$10/GB — consumer DDR5 back above 2014 levels, a decade of deflation erased — and for the first time the cause isn’t a fab accident or a demand blip but a structural reallocation of wafers to AI memory. Whether this is the biggest-ever bump on the old curve, or the end of the curve, is kill-switch #1’s question in long-run form.
No new long-run historical anchor changed the 2001–2026 curve. July reporting reinforces the affordability ceiling: consumer demand is reacting to 2026’s multi-fold rise in memory cost per GB.
Series construction & honesty labels. 2001–2023 [MODELED/approx]: capacity-weighted street prices for mainstream DDR modules, following the industry-standard long-run series convention (McCallum / Our World in Data lineage): ~$180 (2001, DDR1) → ~$90 (2005, DDR2) → ~$12 (2010, DDR3) → ~$4.50 (2015, DDR4) → ~$8 at the 2018 supercycle peak → ~$3.50 (2019) → ~$1.60 at the 2023 glut trough (DDR4/early DDR5). Annual points between the named anchors are interpolated on the same series convention; point values are approximations of a noisy retail distribution, good to ±30% — the shape is the data, not any single point. 2024–2026 [cited]: the tail is anchored to reported moves — DRAM and NAND prices up more than 300% since 2023, with TechInsights projecting continued increases into 2027; DRAM/NAND contract prices jumped 90–95% QoQ in Q1 2026; Gartner projects a 130% year-on-year DRAM price rise for 2026, and even legacy DDR4 — no longer used in phones — is spiking, a signal of how distorted the market has become. Mid-2026 mainstream DDR5 lands ~$9–12/GB at street level (~$300+ for a 32 GB kit that was ~$90 in 2024). Why it matters here: every prior bump on this curve mean-reverted as supply caught up — the bet embedded in memory-maker valuations (§04, kill-switch #6) is that this one doesn’t, because the marginal wafer now has a structurally better-paying customer (§05·C·G, §06·D·W). The falsification path runs through kill-switch #1 (§02·D): the 3Q26 contract-price deceleration (§03) is the first data point of the answer. Modeled series + cited tail — not investment advice.
The memory rally has a leverage story, and it's concentrated in Korea — home of Samsung and SK Hynix, and one of the most retail-leveraged equity markets on earth (the local term for debt-fueled trading is bittu). Margin debt hit a 20-year high in 2026, retail piled into the two chip giants, and on May 27, 2026, Korea launched its first-ever single-stock leveraged ETFs — 2× products on Samsung and SK Hynix that drew billions in days. This is the most direct measure of how much risk retail is putting on the memory trade.
The leverage story worsened: the KOSPI fell 4.9% on Jul 7 and regulators highlighted single-stock leveraged ETFs as a potential volatility amplifier. Samsung and SK hynix together remain an unusually concentrated share of the index.
Six metrics that together gauge whether Korea's retail-driven, leverage-fueled rally is overheating, each over the trailing ~12 months. The composite score blends them into one read; the small charts show how each got there. Note the March spike in every stress metric — that was the Iran-crisis crash (KOSPI −12% in a day, its worst ever) and the forced-selling cascade that followed.
Margin debt, volatility, and speculative ETF flows are all at or near records, and regulators have stepped in to curb leverage. Yet the rally rests on genuine record chip profits — so this reads as a stretched bull market with high unwind risk, not (yet) a pure bubble. The composite is a constructed index, not an official measure.
Dashed line on each chart = the metric's historically "normal" level. Heat flag reflects the latest reading vs that normal band. The composite score weights all six equally and is our construction for illustration, not a published index.
Assets under management in the 2× daily-leverage ETFs tied to each memory maker. Note the radically different ages: Micron's MUU has traded since Oct 2024; the Samsung and SK Hynix products are days old (Korea's first-ever single-stock leverage ETFs, launched May 27, 2026), so their AUM is a debut snapshot, not a track record. Bars are scaled to MUU's ~$5.4B.
The composite overheating score is a constructed index (six metrics, equally weighted, normalized to each metric's historical range) — an illustrative synthesis, not an official or standardized measure. Underlying anchors (real): margin loan balance hit a record ₩36.6T on May 15 when the KOSPI touched 8,000 (Korea Financial Investment Association); the VKOSPI averaged 50.3 in 2026 vs a historical 18.8, hitting 65.5 on May 21 (normal ≈20, >30 heightened, >40 extreme); forced selling reached ₩91.7B on May 18, the largest since July 2023; the KOSPI swung from a 5,288 record (Feb 3) through a −12% single-day crash in March (its worst ever, ~₩625B wiped) to 7,815 (May 21, +8.42%); foreign investors sold a record ₩21.14T in Feb 2026 and ~$13.2B in one May week; Korean retail poured ~$40B into US leveraged ETFs in 2025 ($7B in December alone), then ₩3.87T into the new domestic 2× chip ETFs in three days. Regulators (FSS/FSC) and brokerages (KB, Mirae, Toss, KakaoPay) imposed mandatory training and margin curbs. Bloomberg called the KOSPI the world's most volatile major index; Citi flagged "exuberance" and took profits. The 12-month series are monthly approximations calibrated to these anchors. ETF AUM (real): MUU ~$5.4B (Direxion, launched Oct 2024); KODEX/TIGER Samsung & SK hynix 2× Leverage launched May 27, 2026 — debut net assets ≈ ₩1.75T (Samsung) and ₩2.0T (SK hynix). Won→USD ~₩1,495/$. Sources: KOFIA, Korea Exchange, Bloomberg, CNBC, UPI, Seoul Economic Daily, Digital Today, ETF.com, Direxion. Leveraged ETFs are short-term trading tools, not buy-and-hold investments — and this is not investment advice.
A deep-dive on the single product that best embodies the leverage story above: the KODEX SK hynix Single-Stock Leverage ETF — the largest of Korea's first-ever single-stock 2× leveraged funds (launched May 27, 2026). It seeks twice the daily return of SK hynix's share price. Retail money flooded in, AUM led the entire category within a week — and then SK hynix fell ~14% over two sessions and the fund dropped ~26%, dragging essentially every holder underwater. It's a near-perfect case study of the overheating dynamics this dashboard tracks: huge leveraged retail inflows into a single AI-memory name at the top, then a violent unwind amplified by 2× exposure and negative compounding.
The Korean 2× products suffered another sharp mark-to-market hit during the Jul 7–8 semiconductor selloff. Separately, SK hynix’s U.S. ADR debut triggered a wave of U.S. daily-leveraged ETF filings, extending the same leverage structure to Nasdaq.
KODEX won the asset race (₩2.23T, the category's largest) on Samsung Asset Management's distribution muscle. But the product did exactly what regulators warned: after a +29% debut week it gave back ~26% in two sessions (June 4–5) on a ~14% SK hynix drop, pushing all holders since launch into losses. Negative compounding means it will lag 2× the cumulative move over any volatile stretch. Useful as a short-term trading tool; structurally hostile to holding.
Net assets (bars, left axis) and fund price (line, right axis) since the May 27 listing. Note the timeframe: this product is only ~2 weeks old, so this is a since-inception daily tracker, not a 12-month history (a 12-month series is impossible — it didn't exist before May 27). AUM ballooned on relentless retail net buying even as the price round-tripped and then cratered.
Real anchors: Korea's first single-stock 2× leveraged ETFs listed May 27, 2026; 16 single-stock leverage/inverse products debuted that day with combined first-week net assets ≈ ₩6.75T ($4.89B) and ₩48.7T cumulative trading value. KODEX SK hynix Single-Stock Leverage led on assets at ₩2.227T ($1.61B) — ~₩850B ahead of TIGER SK hynix (₩1.370T, $993M); KODEX debut-day net assets were ~₩1.154T, fee 0.29%. Debut-week return vs NAV ≈ +29% (KODEX SK hynix +29.13%; SOL +29.21% led). Cumulative net retail buying of KODEX SK hynix reached ₩2.0425T (May 27–Jun 5), seven straight sessions of net buying; TIGER SK hynix ₩1.97–2.08T. Then a two-day rout: June 4–5 the SK hynix 2× products fell ~20% then more, ~26% over two days (KODEX −26.16% from ₩29,055→₩21,455; TIGER −26.38%; 1Q futures −27.90%), on SK hynix ~−14%, "all holders since launch now in losses." Regulators (FSC/FSS) flagged negative-compounding and rebalancing risk and deem these short-term-speculation only; concentration in Samsung+SK hynix (a large share of the KOSPI) is itself seen as amplifying index volatility. AUM figures move daily with both flows and price; the since-launch daily series here is calibrated to these reported prints. Then the whipsaw continued: June 8 the KOSPI plunged 8%+ intraday (the 16 single-stock leveraged/inverse ETFs lost 10.3% of NAV in a session) before June 12 ripped ~10% higher to 8,430 — a 2× product round-trips ~±25% on such days, which is the negative-compounding grinder in action. Won→USD ≈ ₩1,383/$ at report. Sources: Korea Exchange, Seoul Economic Daily, Bloomingbit, BigGo, KED Global, TradingKey. Leveraged single-stock ETFs are high-risk, short-term instruments subject to severe loss and negative compounding — this is not investment advice.
The investable universe, anchored to the Roundhill Memory ETF (DRAM) — the first pure-play memory fund (launched April 2, 2026), holding only companies that draw 50%+ of revenue from memory. Its roster is the spine of this directory.
Market close Jul 10: MU $979.30, SNDK $1,915.92, WDC $582.59, STX $910.34. Samsung estimated ₩89.4T Q2 operating profit; SK hynix ADRs opened 14% above offer; Micron expanded planned U.S. investment to >$250B.
The integrated giants — the only three firms that span HBM, DRAM and NAND, and together ~73% of the DRAM ETF:
The rest of the roster — NAND specialists, the hard-drive oligopoly, and China's challengers:
By the numbers — latest-quarter net income, valuation and growth. The memory makers trade at strikingly low multiples for their growth (single-digit forward P/Es, PEG ratios near zero) — the market still pricing them as cyclicals even as AI demand drives record profits. ● live
| Company | Latest Q net income | Fwd P/E | Fwd PEG | Annual rev growth |
|---|
The most recent Wall Street rating actions on the memory & storage names — upgrades, downgrades, initiations and price-target moves over the trailing twelve months, newest first. This list attempts to refresh live; opened as a plain file it shows the compiled baseline (refreshed Jul 10 2026, including the latest BofA action).
Added BofA’s Jul 10 Micron update: Buy maintained and target raised to $1,550 after the >$250B U.S. investment announcement. The ratings list remains a sampled action log, not a complete consensus database.
"PT" = 12-month price target. Ratings reflect each firm's own scale (Buy/Overweight/Outperform ≈ bullish; Hold/Neutral/Equal-Weight ≈ neutral; Sell/Underweight ≈ bearish). Korean & Japanese targets shown in local currency. This is a sampling of notable actions, not every rating; figures are approximate and time-stamped to the action date. Context: Micron's FQ3 print (Jun 24 — record $41.5B revenue, $25.11 EPS, ~$50B next-quarter guide, $22B in customer commitments) set off the densest target-raise wave of the cycle, with the Street high running from ~$1,100 to $2,200 (Melius) in days and SanDisk's high hitting $3,000 (Bernstein). Note the split character: several are price-target raises on maintained ratings rather than upgrades, and Goldman pointedly lifted its target to $1,100 while keeping Neutral — stronger fundamentals, but wary the rally already prices them in. On the bear side, Michael Burry (Scion) disclosed a Micron short and Morningstar flagged 20–30% downside risk (see §04·D·S). Not investment advice.
Micron (MU) is the most liquid pure-play way to trade the memory thesis, and its options market is where positioning and fear show up first. This reads the key sentiment gauges — put/call ratios, implied volatility, the expected move, and unusual activity. Options data is intensely time-sensitive (chains reprice every second), so this is a dated snapshot that rechecks for the latest on load; opened as a plain file it shows the last compiled values. Every metric is explained — and options are a high-risk instrument, not a recommendation to trade.
The options dashboard now anchors interpretation to MU’s Jul 10 close of $979.30. Volatility remains elevated after the late-June earnings gap, the July semiconductor drawdown and Micron’s new capex announcement.
Zooming out from Micron to the whole Korean trade: the iShares MSCI South Korea ETF (EWY) is the most liquid US-listed way to play (or hedge) Korea's memory-led rally. Tracking its price against total call vs. put open interest reveals positioning — and the tell is clear: put open interest has overtaken call open interest even as the ETF ran to records, i.e. investors increasingly paying for downside protection. Then EWY dropped ~14% in early June (≈$204 → ≈$176), exactly the kind of unwind that hedging anticipated.
Options data are dated end-of-day aggregates, not live exchange quotes. Jul 10 anchors: MU $979.30; aggregate IV 94.45%; Barchart IV rank 80.25% and historical volatility 112.65%; volume put/call 0.86; AlphaQuery 90-day open-interest put/call 1.2575; reported option volume about 954.3K contracts. The 30-day expected-move illustration is calculated from annualized IV and spot, not a forecast. Sources: OptionCharts, Barchart, AlphaQuery, OptionSamurai and market-volume reporting. Options involve substantial risk; not investment advice.
Options metrics are dated snapshots, not live exchange data — every value reprices continuously during market hours and is stale within minutes. Anchors (refreshed Jul 10 2026, vintages disclosed per figure — spot itself is printing inconsistently across delayed feeds amid the post-FQ3 whipsaw, ~$940–$1,130): session put/call volume ≈ 1.00 on ~720K contracts (≈360K puts vs 361K calls in a single selloff session, early Jul) — up from ~0.91 in mid-June, a visible hedging bid arriving with the Jul 1–2 ~10% drawdown; put/call open-interest ≈ 1.32 (Aug-21 monthly chain, May-vintage OI); 30-day mean IV ≈ 108% (Jun 23) versus ~70% pre-earnings in January — a full regime shift, with Rule-16 implying ~5.6% daily moves on the Aug chain. Chain geometry tells its own story: max pain ≈ $660, peak call OI at the $1,000 strike, peak put OI at $300 — strikes set before the June melt-up, so the chain’s center of gravity sits far below spot; dealer positioning simply hasn’t rolled up with a stock that ran ~380% off its $201 Nov-2025 low. Ratios and IV vary by expiration and by the second; the figures here illustrate the method and current regime, not a tradeable quote. Sources: Barchart, Fintel, Macroaxis, Stock Options Channel, AlphaQuery, CBOE-style conventions. Options involve substantial risk of loss and are not suitable for all investors. Nothing here is investment advice.
Where Wall Street and Seoul see these six memory names heading over the next 12 months. Each card shows the current price, the consensus and the high/low target range, the implied upside, and the specific recent calls behind it. A live caveat up front: targets are revised constantly in a fast-moving cycle, and for stocks that have multiplied this year the aggregators disagree wildly — so the most recent named-firm targets matter far more than blended "consensus" figures that lag. Korean targets are in won; everything is a dated snapshot.
Micron’s current aggregator consensus is roughly $1,264–$1,311, with published highs near $2,000; BofA’s latest target is $1,550. Wide dispersion remains the key signal, not the exact average.
Jul 12 reconciliation: MU closed Jul 10 at $979.30. Current aggregators cluster near $1,264–$1,311 with published highs near $2,000; BofA raised its target to $1,550 on Jul 10. The longer chronology below preserves dated actions and may contain older spot references. Price targets are analyst opinions with a ~12-month horizon, revised constantly — treat these as a dated snapshot (refreshed Jul 10 2026), not current quotes. A key honesty point: aggregator "consensus" figures are badly inconsistent for these names because many stale targets haven't caught up to stocks that have multiplied — for Micron the range now spans a low near $249 to a high of $2,200 across 43 analysts, a spread that reflects genuine disagreement about how to value a transformed-but-still-cyclical business. Anchors used (current price · notable recent calls, all post-FQ3): Micron ~$1,130 (Jul 6, after a sharp two-day chip selloff Jul 1–2) · the $100B SCA backlog triggered a target stampede — Melius/Ben Reitzes doubled to $2,200 (Street high, from $1,100), DA Davidson $2,000 (from $1,500), Susquehanna $2,000, Cantor $2,000, with JPMorgan's near-tripling among the most dramatic; Erste upgraded to Buy; consensus ~$1,338 (43 analysts), Strong Buy. Bears: Michael Burry (Scion) disclosed a short, and Morningstar's Lorraine Tan warned the biggest memory names could give back 20–30%. Samsung ~₩330,000 · Nomura ₩590K, Korea Investment ₩570K, Shinhan ₩550K, Eugene ₩500K; Buy. SK hynix ~₩2.01M · Nomura ₩4.0M, Korea Investment ₩3.8M, Shinhan ₩3.8M, Eugene ₩3.2M; Buy (ADR listing planned Jun–Jul 2026). SanDisk ~$1,802 (off 11% Jul 2) · BofA raised to $2,500 (Jul 1, from $2,100, NAND imbalance through 2027), Mizuho $2,200; data-center revenue +645% YoY; Strong Buy (Zacks #1). Seagate ~$860 (off 7% Jul 2) · Mizuho $1,090 high, consensus ~$960; Strong Buy. Western Digital ~$626 · BofA raised to $732 (Jul 1, Street high), Mizuho $685, JPMorgan $650; Goldman initiated at Hold (Jul 5); consensus ~$560; Buy. A stock can and does trade above its consensus target (as MU has), which usually means targets are mid-revision. Korean won targets convert roughly at ₩1,490/$. Sources: Benzinga, TipRanks, S&P Global / stockanalysis.com, ChartMill, Seoul Economic Daily, Nomura, Korea Investment & Securities, Evercore ISI, BofA, Cantor Fitzgerald. Not investment advice.
A revealing internal contradiction in the memory trade: even as Micron surged ~790% in 52 weeks, short interest climbed steadily through 2026 to multi-year highs (~41.6M shares, 3.68% of shares out by late June). Meanwhile sell-side sentiment is overwhelmingly bullish (consensus Strong Buy, targets escalating toward $2,000) — yet insiders are net sellers — and as of Jul 2, Michael Burry (Scion) has disclosed a short position in Micron, amid a sharp ~10% two-day chip selloff. That's a genuine three-way tension: momentum bulls (targets now to $2,000) vs short sellers betting "too far, too fast," with management quietly trimming. This section maps all three. Honesty note: short-interest figures are anchored to NASDAQ-sourced reporting; the historical trajectory is interpolated between dated readings.
No newer exchange-reported short-interest settlement replaced the late-June reading. The section keeps the latest reported share count and separates it from daily price/volume data.
Consensus Strong Buy · avg PT ~$628 (stock trades well above it — targets mid-revision)
Provenance & the honesty line. Short interest [anchored — NASDAQ-sourced]: ~41.59M shares / 3.68% of shares outstanding (stockanalysis, Jun 27 2026); a reporting period rose 35.24M→37.55M = 3.34% of float, ~1 day to cover on ~55M avg daily volume (Benzinga); ~37.3M / 3.32% of float in late May, after +15.9% then +2.6% jumps in April, "near the highest levels seen in years… rising steadily through 2026" (Barchart/Yahoo, May 23 2026). Days-to-cover is low (~1) because MU is extremely liquid, so a classic squeeze is less likely than the raw share count suggests. Sentiment [cited]: consensus Strong Buy — of 41 analysts, 31 Strong Buy / 5 Moderate Buy / 5 Hold; average PT ~$628 (stock already above it); Street-high targets escalated through 2026: $1,100 → Wedbush $1,400 → KeyBanc $1,600 (from $600) → J.P. Morgan $1,600 → NZ/Bolton $1,650 → Susquehanna $2,000 (Jul 1, from $1,750) / Cantor $2,000 (Jun 29) / Phillip $1,870; consensus ~$965→~$1,486 (Barchart, TipRanks, Simply Wall St, TheStreet). Burry short [cited, Jul 2]: Scion Asset Management disclosed a bearish position (TipRanks/CNN Markets), coinciding with a ~10% two-session MU/SNDK drawdown on a broad chip rotation — the highest-profile bear yet against the name. Insider counterweight [cited]: insiders sold ~$112M more than they bought over 12 months; CEO Sanjay Mehrotra's direct holding fell from ~1.28M shares (Dec 2024) toward ~0.95M (Simply Wall St). Fundamentals backdrop (updated — FQ3 reported Jun 24 2026): a blowout — revenue $41.46B (up from $23.9B in FQ2 and $9.3B a year ago, ~4.5× YoY), non-GAAP EPS $25.11 on ~84.9% gross margin, all above the high end of guidance; the stock jumped ~14.6% on the print. DRAM was $31.3B (76%) and NAND $9.9B; data-center revenue hit $25B in the quarter (enterprise SSD $5B); operating cash flow was $25.4B and adjusted free cash flow a record $18.3B; the board raised the dividend 30%. FQ4 guidance is a record $50.0B revenue, ~86% gross margin, and $31.00 EPS. HBM3E and HBM4 are fully booked through calendar 2027 with demand into 2028. The bear case is now valuation / memory cyclicality / the explicitly guided "meaningful moderation in the rate of price increases" after FQ4 — not current results (which keep setting records). [FQ2 reference: $23.9B rev / $12.20 EPS.] Modeled [interpolated]: the short-interest and sentiment trajectories between dated readings — bi-monthly SI prints exist but a continuous public time series doesn't, so the curve shows shape through anchors, not every print. The price line is schematic to match the reference image's arc (the dashboard's live MU price lives in §04). On the reference image (Earnings Whispers): it shows a Sentiment line + Short Interest band; the circled right-edge spike to ~40M aligns with the ~41.6M NASDAQ figure. Sources: stockanalysis.com, Benzinga, Barchart/Yahoo Finance, TipRanks, Simply Wall St, NASDAQ short-interest data. Not investment advice.
The memory super-cycle now has a pure-play vehicle: the Roundhill Memory ETF (DRAM), launched Apr 2 2026, holding Samsung / SK hynix / Micron (≥50%-of-revenue-from-memory rule). Its asset-gathering pace has been so extreme it belongs in the same conversation as the fastest ETF launches in history — the spot-crypto giants. This chart races AUM by days since launch, so funds that launched years apart can be compared on equal footing. The honest caveat: the milestone points (●) are anchored to cited reporting; the connecting curves are modeled interpolations — daily AUM histories aren't fully public, so read the shape and ranking, not every point.
Roundhill DRAM was reported around $25B AUM by Jul 6 and closed Jul 10 at $63.04. The new 2× DRAM ETF RAM reported about $779M AUM after launching Jun 24.
Provenance & the honesty line. Anchored milestones [cited]: DRAM (Roundhill Memory ETF, CBOE:DRAM, launched Apr 2 2026) — $1B in 10 trading days, $6.5B in ~36 days, $10B in 43 days, ~$20B by mid-June 2026 (~$17B early June); ~79% return since inception (cryptobriefing, US News, ETF.com, 24/7 Wall St, stockanalysis, Roundhill). IBIT (iShares Bitcoin, launched Jan 11 2024) — $10B in 34 days, ~$50B by ~11 months (Dec 2024), $70B in 341 days (5× faster than GLD's 1,691), then a climb to ~$99–100B by early Oct 2025 (aided by a ~160% BTC rally to ~$125K) before its first-ever monthly outflow in Nov 2025 (−$2.3B) pulled it back toward ~$82–88B (ETF.com, iShares 2025 trends, Benzinga/Bloomberg, cryptonews). IBIT's mid-curve points ($18–21B through 2024, the Oct-2025 peak, the Nov dip) are modeled through those cited monthly anchors. FBTC $10B in 54 days; ETHA (iShares Ethereum, launched ~Jul 2024) $10B in 251 days with a $5B→$10B sprint in 10 days; JEPQ (JPMorgan Nasdaq Equity Premium Income) $10B in 444 days (Eric Balchunas / Bloomberg "five fastest to $10B"; Cointelegraph, AInvest). Modeled [interpolated]: every point between the cited milestones — full daily AUM curves aren't public, so the lines are smooth interpolations through anchored points, not realized daily data. A genuine source conflict, surfaced not hidden: ETF.com called DRAM "the fastest ETF in history to reach $10B" (43 days), yet IBIT reached $10B in 34 days — so DRAM is not faster to $10B by that count. The most defensible reading: IBIT holds the outright $10B speed record (34d); DRAM is the fastest non-crypto / thematic equity ETF and among the fastest overall — the "fastest ever" phrasing likely reflects a category or re-measured basis. Apples-to-oranges caveat: crypto ETFs' AUM is inflated by underlying price rallies (IBIT rode BTC +160%), not just inflows; DRAM's holdings also rallied hard. AUM growth ≠ pure inflows. The "ETF Omen": niche thematic funds have a historical tendency to launch near cycle peaks — worth remembering before reading DRAM's pace as pure validation. Sources: ETF.com, Bloomberg (Balchunas), cryptobriefing, US News, 24/7 Wall St, Cointelegraph, AInvest, stockanalysis, Roundhill. Not investment advice.
The riskiest corner of the flows story just became one of the biggest: the global 2×-leveraged memory complex. What began as a pair of US single-stock funds is now a three-market phenomenon — the US pair (MUU, SNXX), Hong Kong’s CSOP pair on SK hynix and Samsung, Korea’s sixteen single-stock leveraged/inverse ETFs launched May 27, and now basket leverage (RAM, 2× the DRAM ETF, launched Jun 24). Global single-stock L&I assets doubled from <$30B to >$60B in six weeks (Goldman), the CSOP SK hynix 2× (~$16.8B) is now the world’s largest single-stock leveraged ETF — the largest ETF in Hong Kong, period — and the Korean products drive up to 60% of daily turnover in the underlyings. On Jun 23 the tail wagged the dog: an FSS warning cascaded into Samsung −12.3% / SK −12.5% (worst day since 2008) and Micron −13%. Two of the long-window funds below are direct leveraged bets on names in this dashboard — MUU (2× Micron) and SNXX (2× SanDisk) — so their asset swings are a high-beta read on memory-trade conviction. The other two, BITX (2× Bitcoin) and ETHU (2× Ether), are the crypto comparison. This tracks AUM / net assets over a Jun 2023 → Jun 2026 window (BITX's launch onward), with monthly data points anchored to fund quotes/filings. Honesty note: current AUM values are from fund quotes/filings; the monthly path is anchored to dated observations with interpolation between — and leveraged-ETF NAV swings on both flows and the amplified price of the underlying.
The U.S. leveraged-memory complex expanded again around SK hynix’s Nasdaq debut, while Korean products experienced severe volatility. AUM comparisons now need to distinguish U.S. funds, Hong Kong funds and Korea-listed single-stock products.
Weekly-chart provenance. Anchors: global single-stock L&I <$30B at the start of April → >$60B by May 27 (Goldman Sachs / Chris Lucas via BigGo); CSOP SK hynix 2× ~$5.38B on May 7 (overtaking the 2× Tesla fund as world's largest, Seoul Economic Daily) → ~$16.8B by Jun 23 (ETF.com); CSOP Samsung 2× ~$1.65B mid-May (TradingKey — a single dated print, hence the flat dashed line); Korea's 16 funds $3B day one (May 27, ETF.com) → >$9B by Jun 23 (ETF.com, KuCoin; 92% retail); MUU ~$1.1B late Jan → ~$5.9B mid-June (ETF Database); SNXX ~$2.7B late Feb → ~$3.9B mid-June (prior section anchors). Event flags: May 26–27 — Micron and SK hynix cross $1T market cap within ten hours (Samsung crossed May 6) and Korea's 16 funds launch; Jun 22–23 — FSS governor's public criticism ("did little more than enrich securities firms"), then Samsung −12.31% / SK −12.47% / KOSPI −9.99% / MU −13%. Everything between anchors is interpolation; everything after Jun 23 without a print is dashed. Not investment advice.
| Vehicle | Market | Exposure | Status · scale |
|---|---|---|---|
| MUU · Direxion 2× MU | US | 2× Micron | ~$5.9B (mid-Jun) — the original memory-lev trade |
| SNXX · Tradr 2× SNDK | US | 2× SanDisk | ~$3.9B — fastest single-stock launch on record (Jan '26) |
| RAM · Roundhill T-REX 2× DRAM | US | 2× the memory basket (MU+Samsung+SK+SNDK) | Launched Jun 24 — today's only US leveraged route to Samsung/SK |
| 7709 · CSOP SK hynix 2× | Hong Kong | 2× SK hynix | ~$16.8B — world's largest single-stock lev ETF; HK's largest ETF |
| 7747 · CSOP Samsung 2× | Hong Kong | 2× Samsung Electronics | ~$1.65B (mid-May print) |
| Korea 16 · KODEX, TIGER, et al. | Korea | 2× long & −2× inverse, Samsung & SK | >$9B in 4 weeks · 92% retail · up to 60% of underlying turnover · FSS "regret" |
| T-Rex 2× SK hynix (REX) | US | 2× the SK hynix ADR | Filed — pursuing listing; the ADR itself begins trading Jul 10 |
| Leverage Shares 2× Memory | US | 2× the DRAM ETF (RAM competitor) | SEC registration filed May '26 |
Provenance & the honesty line. MUU — Direxion Daily MU Bull 2X (2× Micron), launched Oct 10 2024, 1.06% ER; ~$100M→~$400M by Nov 2025 (+$148M net flows in a month; ~378% YTD return), crossed $1.1B late Jan 2026 (one of ~7 single-stock ETFs over $1B), then went parabolic on Micron's rally to ~$5.9B by mid-June 2026 (ETF Database 1-yr net AUM change ≈ +$5.86B; NAV ~$972/share) — per Direxion/ETF Trends, ETF.com, ETF Database, AAII, SEC. SNXX — Tradr (AXS) 2× Long SNDK (2× SanDisk), launched Jan 26–27 2026, 1.49% ER; hit $650M in 24 days (fastest single-stock-ETF launch by avg AUM/day on record), ~$2.7B by late Feb, ~$3.9B by mid-June 2026 — per Tradr/PRNewswire, stockanalysis, Robinhood, Kraken. BITX — Volatility Shares 2× Bitcoin (first US leveraged crypto ETF), launched Jun 27 2023, ~2.38% ER; grew through the BTC bull market to a multi-billion peak (~$3B+ in late 2024/early 2025), then round-tripped — a ~76% one-year total-return loss and a peak-to-now AUM decline of ~⅔, to ~$1.0B by mid-2026 (1-yr net AUM change ≈ −$2.05B; NAV ~$12 vs 52-wk high ~$69) — per Yahoo, stockanalysis, ETF Database, Kraken. ETHU — Volatility Shares 2× Ether, launched Jun 4 2024, 2.67% ER; ran up to ~$1.4B in early 2025 then suffered a ~74% YTD drawdown to ~$730–790M by mid-2026 (NAV ~$14 vs 52-wk high ~$189) — per Yahoo, MutualFunds, Dividend.com. Monthly points [interpolated]: the per-month values between cited observations — full daily AUM histories aren't public, and leveraged-fund AUM moves on flows + the 2× mark of a volatile underlying, so monthly points show plausible shape through anchored dates, not realized daily data. A note on the source image: this section was requested from a chart whose dollar labels (e.g. MUU $19.2M) didn't match current filings — I rebuilt from current quote/filing AUM instead of tracing it. AUM ≠ inflows for leveraged funds even more than for spot ones: a doubling underlying doubles the leveraged exposure mechanically. Sources: ETF Trends/Direxion, Tradr/PRNewswire, Volatility Shares, Yahoo Finance, Robinhood, Kraken, stockanalysis, AAII, ETF Database, SEC filings. Not investment advice — and these instruments are especially unsuitable for non-traders.
HBM stacks DRAM dies vertically and links them with through-silicon vias — 5–10× the bandwidth of ordinary GDDR. Each generation is matched to a class of AI accelerator.
SK hynix has shipped 12-high HBM4E samples at up to 16 Gb/s per pin. SPHBM4 adds a cost-oriented branch below conventional 2048-bit HBM4 packaging, so the roadmap now has both performance-max and package-cost paths.
What a gigabyte of each HBM generation actually costs — and the single most important caveat on this entire page: HBM has no transparent market price. Unlike DDR5 (which has published DRAMeXchange spot & contract prices), HBM is sold only through confidential long-term contracts between three suppliers and a handful of buyers, bundled and volume-dependent. Every number below is an analyst triangulation from earnings commentary, teardown cost models, and industry reports — directional, not a quoted price. The pattern that is reliable: each generation costs more per bit (more stacked layers, finer TSV pitch, lower yield), and HBM sits at a large premium to commodity DRAM. The newest hard anchor: on June 5, SK hynix finalized 2026 HBM4 price/volume terms with NVIDIA at >50% above HBM3E — the first concrete HBM4 price signal, replacing earlier guesswork.
No transparent HBM spot market has emerged. SPHBM4 could lower total package cost by avoiding large interposers, but it does not establish a new public raw-stack price; the cost ranges remain estimates.
Note the squeeze at the right of the conventional-DRAM bar: DDR5 itself is now ~$10–12/GB in this shortage, up from ~$3–4 a year ago. That's why HBM3E's premium over DDR5 has collapsed from ~4–5× (early 2025) toward ~1–2× by end-2026 (TrendForce) — not because HBM got cheaper, but because commodity DRAM caught up.
Provenance — read this before citing any number. There is no public HBM spot or contract index; the three suppliers (SK hynix, Samsung, Micron) sell HBM under confidential long-term agreements, so all figures are analyst estimates triangulated from earnings calls, teardown cost models, and trade-press reports, and they vary widely by source, buyer, volume and quarter. Per-stack anchors (Silicon Analysts, Apr 2026): HBM3 ≈ $200 / 24 GB stack (~$8–10/GB), HBM3E ≈ $300 / 36 GB stack (~$8–13/GB), HBM4 ≈ $500 / 48 GB stack (est., ~$10–14/GB; pre-volume). HBM3E reportedly peaked at ~$17–20/GB in H1 2025 at the demand peak (Silicon Analysts citing TrendForce / Goldman Sachs / SemiAnalysis), then 2026 contracts were struck lower before a reported ~20% HBM3E price hike for 2026 (TrendForce / Chosun Biz). HBM4 (June 5, 2026): SK hynix finalized 2026 HBM4 price & volume with NVIDIA at >50% above HBM3E per Korean press — implying ~$17–19/GB on the HBM3E midpoint, the first negotiated HBM4 anchor (prior figures were pre-volume estimates). Legacy HBM2/HBM2E ($/GB) are directional single-source estimates — public data is sparse before the 2022 AI inflection. Baseline: server DDR5 ≈ $1.50/Gb (~$12/GB) currently (Counterpoint), elevated by the shortage. Premium dynamic: HBM3E commanded >4× DDR5 in 2Q25, narrowing toward 1–2× by end-2026 as DDR5 spikes (TrendForce). Cost-of-production driver: 1 GB of HBM needs ~3–4× the wafer capacity of DDR5 (Tom's Hardware / TrendForce). System context: a B200 with eight HBM3E stacks carries ~$2,400 of memory, exceeding its logic-die cost (Silicon Analysts). "$/GB" is the practical proxy for cost-per-bit (1 GB = 8 Gb). Sources: Silicon Analysts, TrendForce, Counterpoint Research, Goldman Sachs, SemiAnalysis, Tom's Hardware, KED Global, Chosun Biz. These are estimates of a non-public price. Not investment advice.
Four generations, one family. The similarities are the shared DNA below — every generation is the same fundamental idea: stacked DRAM dies wired vertically with TSVs, sitting on a 2.5D silicon interposer next to the GPU, trading a wide-and-slow bus for GDDR's narrow-and-fast one. The differences are where each generation finds its bandwidth: HBM3→3E pushed pin speed on the same 1024-bit bus; HBM4 is the architectural break — it doubles the bus to 2048-bit (while its per-pin speed actually falls back to HBM3-class), moves the base die from a DRAM process to a logic process, and requires a new PHY and interposer; HBM4E then pushes pin speed again on the doubled bus. Honesty note: HBM4E has no announced product — its figures are projections and are marked as such throughout.
HBM4E sampling at 16 Gb/s per pin is now included in the generation narrative. SPHBM4 is shown as a parallel packaging/interface standard rather than a successor generation.
The tell: HBM4's per-pin speed drops back to HBM3-class (6.4–8 Gb/s spec) — its ~2× bandwidth gain comes from the doubled 2048-bit bus, not the clock. HBM3E and HBM4E are the "speed" generations; HBM4 is the "width" generation.
Provenance & the honesty line. Spec anchors [JEDEC + vendor disclosures]: HBM3 standardized Jan 27 2022 (JESD238): 1024-bit bus as 16×64-bit channels, 6.4 Gb/s/pin → ~819 GB/s per stack; SK hynix mass production Jun 2022 for Nvidia's H100. HBM3E is a vendor-enhanced extension of HBM3, not a new JEDEC generation: same 1024-bit bus, 16 channels / 32 pseudo-channels, pin speed pushed to 8–9.6 Gb/s (Micron's 9.6 → ~1.2 TB/s; up to 12.4 in advanced implementations), 36 GB 12-Hi with a 48 GB 16-Hi announced (SK hynix, Nov 2024), ~2.5× perf/W vs HBM2E, backward-compatible with HBM3 controllers (Siemens EDA design guide, Rambus, Wikipedia). HBM4 ratified Apr 15 2025 (JESD270-4): 2048-bit / 32 channels / 64 pseudo-channels — the doubled bus is the generation break; JEDEC per-pin spec 6.4–8 Gb/s (HBM3-class; Samsung has demoed ~13) → ~2.0 TB/s at 8 Gb/s and up to ~3.3 TB/s in advanced configs; up to 16-Hi with 32 Gb dies = 64 GB/stack; the base die moves to a logic process (12nm FFC+ / 5nm at TSMC), opening near-memory compute; first parts shipped late 2025/early 2026 from SK hynix & Micron; Nvidia Rubin R100 (H2 2026, up to 22 TB/s per GPU) and AMD MI400/MI430X are the first major platforms (Siemens, IntuitionLabs, Spheron, HyperPC, Wikipedia). HBM4E [projection — flagged]: in development for ~2027–28; controller IP already supports up to 16 Gb/s (Rambus), implying ~4.1 TB/s per stack on the 2048-bit bus; Micron's roadmap points to customized logic base dies; no GPU product is announced as of mid-2026 and its specs are not manufacturer-confirmed (Spheron, IntuitionLabs) — every HBM4E figure here is hatched/starred as projected. A source conflict, reconciled: Rambus materials describe HBM4/4E controllers as "backward compatible with HBM3" — that refers to multi-mode controller IP; the physical HBM4 interface is a hard break requiring new PHY, a finer-pitch interposer, and CoWoS-L-class packaging ("you cannot drop an HBM4 module into an HBM3E slot" — Siemens/Kynix/AIChipLink). The table reflects the physical reality. Why it's on-thesis: the width-doubling plus logic base die is part of why HBM consumes far more wafer and packaging capacity per GB (see §05·B share and §05·C cost) — and per Micron's FQ3 call (Jun 24 2026), HBM4 12-high is ramping ~2× faster than HBM3E did, with HBM3E + HBM4 sold out through calendar 2027. Sources: JEDEC (JESD238, JESD270-4), Rambus, Siemens EDA, Spheron, IntuitionLabs, Kynix, AIChipLink, Nevsemi, HyperPC, Wikipedia, Micron FQ3'26 earnings call. Not investment advice.
Two layers, both with surplus/deficit shown in their native units. Memory (DRAM) is in a structural deficit — measured in bits (demand growth outrunning supply growth) — driven by HBM eating a hugely disproportionate share of wafers. All-semiconductor wafers are not in aggregate shortage — measured in wafer-starts/month (kwspm) — but are sharply bifurcated: leading-edge (2/3nm) and advanced packaging (CoWoS) are sold out, while mature nodes sit in glut. The honest caveat up front: wafer capacity cleanly split by end-use is barely published (SEMI segments by device type and node, not application), so segment splits below are triangulated and tagged A anchored / E estimate / T triangulated.
Micron raised its U.S. fab/R&D commitment above $250B through 2035 and added up to $3B for domestic supply-chain development, including financing tied to U.S. silicon-wafer capacity. Near-term 2026 wafer constraints are unchanged; the impact is 2027+.
1 GB of HBM consumes ~3–4× the wafer area of standard DRAM (TSV stacking, bigger die, 50–60% yield). So HBM is a single-digit share of DRAM bits but devours roughly a quarter of DRAM wafers — starving everything else.
Provenance & method. Anchored [A]: SEMI World Fab Forecast — total capacity ~29M wpm (2022) → 33.6–33.7M (2025), +6.6–7%/yr; leading-edge ≤7nm 850K (2024) → 982K (2025) → 1.16M (2026) → 1.4M (2028); China ~⅓ of capacity. TrendForce — 2026 DRAM bit demand +35% vs supply +23%; HBM wafer-input share 18%/22%/30% for 2025/2026/2027; conventional DRAM contract +90–95% QoQ in 1Q26; DRAM CapEx $53.7B→$61.3B (2025→26). Samsung/SK hynix Q1 2026 earnings — ~70% DRAM order fulfillment (35–40% for smaller buyers), ~72%/~70% operating margins. Estimate [E]: Citi (demand +20.1%/supply +17.5%), IDC (+16% supply), CoWoS 13K→35K→~130K wpm (2023→24→26, TSMC guidance), NVIDIA >50% of 2026 CoWoS. Triangulated/extrapolated [T]: the 2022–2025 bit-growth pairs (primary industry-total pairs weren't published — reconstructed from the 2022–23 downturn + 2024–25 recovery narrative), all 2027→2035 projections, and the application-segment wafer splits (SEMI segments by device/node, not end-market). Reconciled discrepancy: one source listed HBM 2024 wafer share at ~5%, which is internally impossible (below its ~8% bit share, when HBM uses more wafers/bit) — this dashboard uses the internally-consistent ~3× ratio (HBM ~14% wafers / ~5% bits in 2024), matching §05·B. Unit trap: SEMI reports 200mm-equivalent; actual 300mm DRAM starts (~2.25M/mo in 2025) are ~½ the 200mm-equiv number (~4.5M) — always check the basis. The super-cycle end-date is contested (relief "2027" to "past 2028"); pricing/fulfillment move monthly. Sources: SEMI, TrendForce, IDC, Counterpoint, McKinsey, Yole, SemiAnalysis, Silicon Analysts, company earnings. Analysis, not investment advice.
The demand engine, by vendor: every major AI accelerator and all the memory on its package or module. Each bar is stacked by memory type — HBM (by generation), on-die SRAM, GDDR, plus the LPDDR5X system memory on Nvidia's Grace/Vera superchips. The merchant GPUs (Nvidia, AMD) and the hyperscalers' own silicon (Google, Amazon, Microsoft, Meta), plus wafer-scale Cerebras and RISC-V Tenstorrent, are all here. Memory per device — not unit volume — is what's exploding.
Accelerator configurations are unchanged, but their memory input assumption is stronger: HBM4E sampling is under way and AWS’s July reservation-price increases show that premium accelerator capacity still clears at higher prices.
Eight companies now design AI accelerators. HBM is the common thread, but the full memory picture is richer: Nvidia's Vera Rubin superchip pairs 576 GB of HBM4 with up to 1,536 GB of LPDDR5X system memory; Cerebras goes the opposite way with 44 GB of blisteringly fast on-die SRAM and no HBM; Tenstorrent uses cheaper GDDR6. Top-end HBM has grown from the H100's 80 GB (2022) toward 1 TB+ per package by 2027–28. Multiply across every vendor's roadmap and the wafer math becomes overwhelming.
Bars are stacked by memory type and scaled to total on-package/module memory — so the LPDDR5X-heavy superchips (GB200/GB300/Vera Rubin) show their full memory pool, and the "GB" figure on each card is the total of all memory types. The chronological view, per-GPU breakdown, and rack-level totals are in the roadmap below. Future/announced parts are marked. Hyperscaler ASIC specs (Google, Amazon, Microsoft, Meta) and the alt-architectures (Cerebras SRAM, Tenstorrent GDDR) are disclosed less fully than merchant GPUs; some capacities are approximate. Sources: Nvidia, AMD, Google, AWS, Microsoft, Meta, Cerebras, Tenstorrent, SemiAnalysis, ServeTheHome.
Every major AI accelerator in release order — Nvidia, AMD, Google, Amazon, Microsoft, Meta, plus alt-architectures Cerebras and Tenstorrent — with the type and amount of all memory on the package or module: HBM, on-die SRAM, GDDR or LPDDR5X. Each card lists peak compute, and rack-scale systems show their full pooled memory. Use the controls below to switch view (per-module vs per-GPU), filter shipping vs announced parts, or switch to log scale so the older & smaller parts stay legible alongside Rubin Ultra & Feynman.
No major vendor pulled in a new accelerator generation after the June roadmap. The memory side advanced: HBM4E samples and SPHBM4 were added as the newest July developments.
Notes: bandwidth figures are per-GPU package (HBM). "Per superchip" rows include the CPU's LPDDR5X because it ships soldered/socketed on the same module and is coherently shared with the GPU(s) over NVLink-C2C. Standalone GPU rows (B200, MI-series) list HBM only — system DRAM is configured separately by the system builder. Capacities reflect top-bin configurations; salvaged/cut-down SKUs ship with less. Hyperscaler ASICs (Google TPU, AWS Trainium) use HBM but disclose less detail. Sources: Nvidia, AMD, Google, AWS, SemiAnalysis, ServeTheHome.
A naming correction first, because it matters: these are Google's TPUs. Broadcom is Google's co-design and ASIC partner — Google owns the architecture and software stack; Broadcom supplies the foundational IP, SerDes/interconnect, and silicon implementation, then coordinates fabrication at TSMC. The two have shipped seven generations together since 2014, under a supply agreement now extending to 2031. Broadcom separately builds custom "XPU" accelerators for other customers (below). So "Broadcom's TPU" is really "the Google TPU that Broadcom helps build." The HBM-per-chip column is the reason TPUs matter to this dashboard: each generation is a growing customer for the same HBM that's in shortage.
Google’s June 2026 TPU supercomputer paper remains the newest consolidated primary-source architecture review; no later TPU generation has been publicly specified.
The trajectory that matters: TPU HBM per chip ran 16 GB (v5e) → 95 GB (v5p) → 32 GB (v6e) → 192 GB HBM3E (v7 Ironwood) → 288 GB (gen-8 inference). Ironwood alone is 6× the HBM of Trillium. Multiply by millions of chips deployed (see §06·C) and Google is one of the largest single consumers of HBM on earth — most of it bought from SK hynix and Samsung, the same suppliers serving NVIDIA.
Broadcom disclosed six named XPU customers as of Q1 FY2026, anchoring a >$100B AI-chip revenue target for 2027 against a ~$73B backlog. TPUs (Google) are one program; the others are distinct custom accelerators. Anthropic's compute runs on Google TPUs, so it appears both as a TPU consumer and a Broadcom customer.
Provenance. Real specs (sourced): TPU v5e 16 GB HBM, v5p 95 GB HBM (7nm), v6e/Trillium 32 GB HBM, v7/Ironwood 192 GB HBM3E @ 7.37 TB/s (6× Trillium, GA late 2025), 8th-gen split into 8t (training) and 8i (inference, ~288 GB) for 2026 — per Google Cloud docs/blog, Introl, Spheron, CloudOptimo, Nevsemi. Customers: Broadcom Q1 FY2026 earnings named six XPU customers — Google (TPU, 7 gens since 2014, deal through 2031), Meta (MTIA), Anthropic (~1 GW TPU in 2026 → ~3 GW in 2027, via Google TPUs), OpenAI (first XPU 2027, 10 GW multi-year deal, 3nm+2nm), plus Apple (new 2026 disclosure) and ByteDance/Fujitsu among named/reported — per Tom's Hardware, CNBC, Jon Peddie, hashrateindex. Projected / unannounced: a 9th generation is modeled in §06·C, but "TPU v9, v10, v11" are not public products — no announced specs, memory, or customer assignments exist. The HBM figures for those rows are illustrative extrapolations (continuing the roughly-doubling-every-2-gens trend), not Google roadmap data, and are visibly hatched. Anyone citing a "TPU v11 memory spec" is citing speculation. Not investment advice.
How many data-center AI accelerators ship — the volume driving all that memory demand. Important honesty note: vendors don't disclose unit shipments, and the in-house hyperscaler chips (TPU, Trainium, Maia, MTIA) aren't sold commercially. So none of this is reported data — it's the most honest available reconstruction from analyst estimates, rack-shipment reports, and revenue. Below: annual totals (Nvidia vs others), then a more speculative quarterly-by-vendor breakdown and a per-specific-accelerator view (B300, GB300, TPU v7 Ironwood, MI350, Trainium 3…). Every figure is an analyst triangulation with a wide error band — the further into per-quarter/per-chip detail, the more uncertain.
No vendor released audited accelerator unit shipments by model. The chart remains a scenario model; July news was used to refresh narrative assumptions, not to create false “actual” units.
A quarterly breakdown by vendor, stacked. This is the most speculative chart in the dashboard — quarterly per-vendor unit counts aren't disclosed by anyone, so every bar is a triangulation from rack-shipment estimates, revenue, and supply-chain reports. The shape (Nvidia dominant but custom-ASIC vendors ramping fast) is well-supported; the exact numbers are not. Click a vendor to toggle.
Approximate full-year-2026 unit estimates for the specific accelerators driving demand. Bars scaled within the whole set. Hyperscaler-ASIC volumes (TPU, Trainium, Maia, MTIA) are internal-deployment estimates; merchant-GPU volumes derive from rack and revenue reports. All are analyst triangulations, not disclosed figures.
Every data-center accelerator from each of the six major vendors, stacked by quarter from 2022 to 2030 — read both the running total and how each generation hands off to the next. These are the dashboard's most speculative charts: per-model quarterly units aren't disclosed by anyone, and beyond mid-2026 it's projection. The wave shape is the insight; the numbers are illustrative. Pick a vendor, toggle Units/Share, click models in the legend to hide them.
On the per-model quarterly charts (2022–2030): these are the most heavily modeled visuals in the dashboard — a reconstruction, not reported data. No vendor discloses per-model unit shipments by quarter, and roughly half this timeline (Q3 2026 →) is a forward projection. Each model is shaped as a lifecycle curve (ramp from launch → peak → decline as the next generation takes over), calibrated so annual totals stay near the figures used elsewhere on this page and so generational hand-offs land at the right times. Real timing anchors used: Nvidia — H100 late 2022, Blackwell late 2024, GB300-over-GB200 in 2H 2025, Vera Rubin in full production mid-2026, Rubin Ultra ~2027–28, Feynman ~2028+; AMD — MI300X late 2023, MI350 in 2025, MI400/Helios in 2026, MI500 ~2028; Google — TPU v7 Ironwood announced Apr 2025 / GA late 2025–26 (internal forecast revised ~2M→~4M units; Anthropic contracted up to 1M TPU chips in 2026, 400K Ironwood in phase one), 8th-gen TPU 8t/8i on TSMC 2nm previewing 2H 2026 with GA targeted late 2027; Amazon — Trainium3 (first 3nm, 144 GB HBM3e) shipping Dec 2025, Trainium4 (NVLink Fusion) due late 2026/early 2027, with ~35% of AWS's ~$100B 2026 capex earmarked for Trainium-family silicon; Meta — MTIA v1 announced 2023, v2 "Artemis" in 2024, with a 300-series roadmap extending through ~2027 (inference-first, internal to Meta's fleet); Microsoft — Maia 100 announced Nov 2023 (limited deployment), Maia 200 (3nm, 216 GB HBM3e) announced Jan 2026 (the least-mature hyperscaler program). Note the hyperscaler chips (TPU, Trainium, MTIA, Maia) are never sold as parts — they're deployed internally and rented via cloud — so their "units shipped" are even more inferred than merchant GPUs (anchored via Broadcom/Marvell rack revenue and cloud-capacity disclosures). Peak heights are anchored to those sources, but exact per-quarter splits are interpolated and the projected generations (Rubin Ultra, Feynman, TPU 9th-gen, Trainium5, MTIA next-gen, Maia next-gen) are scenario, not forecast — real volumes could differ by a wide margin. Read the generational shape, not the precise unit counts. Units are individual chips, not racks or revenue. The four hyperscaler programs differ hugely in scale — Google and Amazon ship multiples of Meta and Microsoft — and summing all six charts gives a total in the same ballpark as, but not identical to, the high-level annual figures elsewhere on this page (they're independent estimates built different ways). Sources: Nvidia/AMD filings & keynotes, Google Cloud/Broadcom, AWS, Meta, Microsoft/Azure, SemiAnalysis, Morgan Stanley, Omdia, TrendForce, Tom's Hardware, The Next Web. Not investment advice.
The root of the whole supercycle: the explosion in AI tokens processed — the raw workload that every accelerator and memory chip ultimately exists to serve. Honesty note: there's no authoritative global token counter. But several providers now disclose real figures — Google especially (9.7T tokens/month in early 2024 → 3.2 quadrillion/month by May 2026), plus Microsoft Azure and others. The bars below estimate total global token run-rate (tokens processed per month, at each quarter-end), built up from those disclosures plus analyst aggregates. The linear scale shows just how brutally recent and vertical the climb has been — the pre-2025 bars almost disappear against the right-hand side, which is the truthful read of an exponential.
No comprehensive global token counter exists. The model is retained, while July evidence—Meta beginning direct model API monetization and hyperscaler capex expectations—supports continued demand but not a precise new token total.
Real disclosed anchor points behind the token estimate: Google — 9.7T/mo (Apr 2024), 480T/mo (May 2025), 980T/mo (Jul 2025), ~1.3 quadrillion/mo (Oct 2025), 3.2 quadrillion/mo (May 2026, I/O). Microsoft Azure — 100T+/quarter through 2025, a record 50T in March 2025. OpenAI — ~6B tokens/min on the API (~260T/mo), plus ~900M weekly active users. A mid-2025 cross-provider aggregate (Tunguz) put the world at ~88 trillion tokens/day ≈ 2.6 quadrillion/month. Projection to 2028: the run-rate is extrapolated from 7 quadrillion/mo (mid-2026) on a decelerating growth curve (~30%/qtr easing toward ~15%/qtr) to ~54 quadrillion/mo by Q4 2028 — roughly 8× over two-plus years. That is an aggressive model, not a forecast; demand could stall on a capex pause or compound faster — the error band widens every quarter to the right. The memory-required chart is a second-order model built on top of the token model (token assumptions × serving-efficiency assumptions), so its uncertainty is compounded — use it for the shape of the argument, not the level. Tokens/month run-rate, not cumulative. Sources: Google I/O & earnings, Microsoft earnings, OpenAI, SemiAnalysis, Tomasz Tunguz, First Page Sage, Similarweb, company disclosures. Not investment advice.
Silicon Data publishes the LLM Token Expenditure Index (ticker SDLLMTK) daily on the Bloomberg Terminal — an expenditure-weighted average of what the whole market pays per million LLM tokens, across frontier APIs, open-weight platforms, and brokered/self-hosted inference (>90% of global inference spend). It's a proxy for the market's marginal willingness to pay for AI, and one macro strategist (Andreas Steno Larsen, Jun 9 2026) called it "the most important chart for the entire market" — because if token spend rolls over, the memory/GPU/datacenter trade this whole dashboard tracks loses its demand engine. Critical honesty note: the actual daily index values are a paid Bloomberg/Silicon Data product — I can't reproduce the proprietary series. The curve below is a schematic reconstruction of the index's publicly-described shape, pinned to a handful of cited public reference points. Treat it as the story of the index, not its values.
No newer public Silicon Data index print with a reproducible time series was found. The section preserves the last anchored reading and labels all subsequent shape assumptions.
Provenance & the honesty line. SDLLMTK is a real, proprietary index — Silicon Data, published daily on Bloomberg Terminal; full history is a paid product (sales@silicondata.com). I have not reproduced the actual series (I don't have the values), so the chart is a schematic of the publicly-described shape, anchored to these cited public statements: per-token price down >90% since 2023 and expenditure ~2× since late 2025 (Torsten Slok / Apollo, via X, Jun 2026); index "more than doubled since December," rose sharply through May 2026, then a downtick/stagnation (Seeking Alpha citing Andreas Steno Larsen, Jun 9 2026; corroborated by Citadel Securities "Tokenomics," Jun 2026, and 36Kr); a public reading ~2.12 with May acceleration (third-party chart commentary, mid-2026). The "stagnation" is Silicon Data's own framing — possibly slowing migration to premium closed models, not a confirmed reversal. The index is expenditure/usage-weighted price (marginal willingness to pay), not token volume and not simple list price; Silicon Data notes it would more precisely be called a "Token Expenditure Price Index." Why it's here: token billing ties AI usage directly to GPU-hours, DRAM bandwidth, and datacenter demand, so a durable roll-over would be an early warning for the memory thesis — exactly the leading indicator this dashboard exists to watch. For the real-time series, see Silicon Data / Bloomberg SDLLMTK. Schematic of a proprietary index. Not investment advice.
One story runs through all four memory types: consumers built the market; data centers took it over. Each chart below splits 100% of that memory type's annual supply by end-use application, from 2010 to today with a projection to 2030. In 2010 every one of these was dominated by PCs, phones, or consumer gadgets. By the mid-2020s — and overwhelmingly by 2030 — the data center is the center of gravity for all of them. Honesty note: like the token-share chart above, these are modeled shares — smooth reconstructions anchored to cited industry reference points (marked in the captions), not a continuously-reported annual series. The dashed line marks where history ends and projection begins.
Apple’s June/July device price increases and reported memory-upgrade repricing support the modeled shift toward higher value per bit even as consumer unit demand becomes more price-sensitive.
By bit consumption. Anchors: server overtook mobile in 2023 (~37.6% vs 36.8%, TrendForce); HBM ~5% of bits 2024; AI/HBM ~20% of DRAM wafers by 2026.
By bit consumption. Anchors: smartphones ~40% / SSD ~25% in 2023; enterprise SSD becomes the #1 segment in 2025–26 (TrendForce).
By bit consumption. HBM didn't exist before 2015 (AMD Fiji). Anchors: AI/ML ~55%+, HPC ~25%, graphics ~12%, emerging ~8% in 2026 (PatSnap/JEDEC).
By capacity (exabytes) shipped. Anchors: nearline ~54% of capacity today → >90% by 2029 (Coughlin); client/consumer collapsing as PCs move to SSD.
Provenance & the honesty line. These four charts are modeled shares — the same epistemic class as the "By Provider" token chart above. No vendor publishes a continuous 2010–2030 annual end-use breakdown by bit/exabyte, so each series is a smooth reconstruction fitted to cited anchor points and the well-documented qualitative arc. Anchors used — DRAM: server DRAM overtook mobile in 2023 at ~37.6% of bits (mobile 36.8%), server the largest segment since (TrendForce); HBM ~5% of DRAM bits / ~20% of revenue in 2024 (TrendForce); AI projected to consume ~20% of DRAM wafer capacity in 2026 (Commercial Times/TrendForce); the 2010–2015 mobile surge and PC decline are well-documented. NAND: smartphones ~40% and SSD ~25% of demand in 2023 (industry reports); enterprise SSD becomes the single largest NAND application segment in 2025–2026 on AI-server demand, with suppliers shifting capacity from client/mobile to data-center SSD (TrendForce, Jan 2026); 2010-era dominance of cards/USB + mobile is well-documented. HBM: first commercial use 2015 (AMD Fiji, graphics), data-center accelerators from Nvidia P100 (2016); by 2026 AI/ML training+inference ~55%+, HPC ~25%, graphics ~12%, emerging (autonomous/edge/networking) ~8% (PatSnap citing JEDEC); early years were graphics/HPC-weighted before AI dominance. HDD: nearline ≈54% of capacity shipped today, projected >90% by 2029 (Tom Coughlin); consumer/client HDD displaced by SSD (flash is "the default choice outside the data center"); 2010 was PC/consumer-dominated before the nearline/cloud shift. The caveats: (1) shares are by the noted unit (DRAM/NAND/HBM by bits, HDD by exabytes) — not revenue, and not unit count; (2) category boundaries blur (e.g. "server" vs "AI server," "graphics" GDDR vs HBM) and different sources slice differently; (3) everything past ~2025 is projection and widens with time; (4) HBM is a subset of DRAM shown separately because its end-use profile is distinct. Sources: TrendForce, PatSnap/JEDEC, Tom Coughlin/Forbes, industry market reports, company disclosures. Modeled shares — analysis, not investment advice.
An AI chip is like a super-fast cook. It can chop a million carrots a second — but the carrots live in a pantry down the hallway, and it can only carry a few armfuls per trip. So the cook mostly just… stands there, waiting for carrots. "Memory" is the pantry and the hallway. Give the cook a bigger pantry right next to the stove and a wider hallway, and it almost never waits. That's the memory wall — and it's why everyone is racing to buy more memory.
Here's the weird part: to write each single word, an AI has to re-read its entire brain — all of its billions of stored numbers — from memory chips sitting next to the processor. The math units are so fast they finish almost instantly, then wait for the next full re-read. So chatbot speed isn't set by how fast the chip does math; it's set by how fast memory can feed it (bandwidth) and how much fits next to the chip (capacity). The proof: Nvidia sold a chip with the exact same math speed as its old one but bigger, faster memory — and AI output nearly doubled. Rule of thumb from this section: generating one word costs as much chip-time as reading ~300.
Precisely: autoregressive decode at batch B has arithmetic intensity ≈ B FLOPs per weight-byte (weight reads amortize across the batch; per-request KV reads never do), against ridge points of ~281 (B200) to ~568 (Rubin) FLOPs/byte — so the tensor-core utilization ceiling ≈ min(1, B/ridge), B is capped by HBM capacity (weights + KV must be resident), and at long context the KV term dominates and pins utilization below 1% at any batch. Prefill is the compute-bound phase; decode is the memory-bound one; measured MFU on H100/Llama-3-70B stays under 20% below B≈100 for exactly the capacity reason. Everything below quantifies this — the roofline chart, the frontier and open-model scenarios, and the 16-prompt verdict table. (The analogies above compress; the numbers below don't.)
The dirty secret of AI inference: the world's most expensive chips spend most of their time waiting. During the decode phase — generating each new token — the GPU must re-read the entire model's weights from HBM for every single token. A 70B FP16 model means ~140 GB read per token. The H100 pairs ~1,979 FP8 TFLOPS of compute with 3.35 TB/s of bandwidth — a 591:1 compute-to-memory ratio — so at low batch sizes the tensor cores are mathematically capped at single-digit (even sub-1%) utilization while they wait on memory. More memory is the fix, through two distinct levers: more bandwidth steepens how fast utilization rises with batch size, and more capacity lifts the ceiling on batch size itself (every concurrent request needs its KV cache resident in HBM). That is the causal engine of this whole dashboard: idle compute is the most expensive thing in the data center, and memory is what un-idles it.
New July work continues to frame decode as a bandwidth-delivery problem. HBM4E raises bandwidth; SPHBM4 attacks package cost; KV-cache compression and in-flash approaches attack bytes moved. None removes the memory wall across all workloads.
DeepSeek-V4 prompt table — derived math. Reference: DeepSeek V4 Pro (49B active of 1.6T MoE, 7 KB/token KV — see the open-weights block above) served batch-1 on an 8×B200 node, FP8 (aggregate ~36 PF dense FP8, 64 TB/s HBM — the node that holds the ~1 TB checkpoint). Per-token: prefill ≈ 2×49e9 ÷ 36 PF ≈ 0.0027 ms/input-token (compute-limited); decode ≈ (49 GB active-expert read + 7 KB×context KV) ÷ 64 TB/s ≈ 0.77 ms/output-token, rising only to ~0.79 ms even at 250K context — the compressed-KV signature. Crossover ≈ 281 input:output, a hardware compute:bandwidth property (hence close to the H100 table’s 295), not a model property. MoE caveat, sharper than dense: batching amortizes the active-weight read, but different tokens route to different experts, so a large batch touches most of the 384 experts — amortization is weaker than for a dense model and real decode stays memory-bound to higher batch sizes. Verdicts are batch-1 per-request; prefill idealized at 100% MFU; token counts illustrative. Not investment advice.
How the estimate is built, and its limits. The mechanism [well-established]: prefill (ingesting the prompt) is compute-bound; decode (generating tokens) is memory-bandwidth-bound — now "the default playbook across nearly every major LLM serving" stack, with disaggregation shipping at Perplexity, Meta, Mistral, and via NVIDIA Dynamo/vLLM/SGLang/TensorRT-LLM. Measured, prefill runs GPUs at 90-95% utilization while decode craters to 20-40%, and prefill saturates tensor cores at 30-45% MFU while decode sits mostly idle waiting on memory bandwidth (Towards Data Science / InfoQ Sept 2025; buildmvpfast; HuggingFace). The governing rule [derived, shown above]: a request's decode-time exceeds its prefill-time whenever its input:output ratio is below the crossover — ~295:1 on H100, ~281:1 on B200 — so unless average prompts read ~300× more than they write, GPU-time is decode-dominated, i.e. memory-bound. Why time ≠ tokens: output tokens cost far more to produce — providers price them at 3:1 to 5:1 over input tokens (e.g. Claude Sonnet $3 input / $15 output per million, a 5:1 ratio), reflecting the sequential per-token generation cost. So even where input tokens dominate by count, output tokens dominate by time and money. Workload weighting [cited anchors, still an estimate]: real mixes span a wide range — a typical support-ticket workload is ~3,150 input / 400 output tokens (~8:1, input-heavy), while high-throughput models like DeepSeek V3.2 show an output-to-input ratio near 1.6× and Llama 4 Maverick around 3× (output-heavy); programming rose from 11% to over 50% of all LLM token usage on OpenRouter by late 2025, and agentic coding workflows average 1–3.5M tokens per task — long, cached, input-heavy contexts by count but with substantial generation. Crucially, reasoning/thinking tokens are billed and processed as output (decode) — reasoning models use 10–20× more tokens — pushing the time-share further toward memory. The batch caveat [bounds the estimate]: at high concurrency decode GEMMs can turn compute-bound — past roughly batch 32 the decode GEMMs become compute-bound while attention stays bandwidth-bound — but the attention/KV reads remain memory-bound, and at long context KV dominates and keeps decode memory-bound at any batch (per the frontier and DeepSeek blocks above). This is the main reason the time-share isn't ~100% memory: heavy-batch, short-context decode and bulk-ingest prefill claim the compute-bound remainder. Bottom line: by the metric that matters for this dashboard — GPU-time, and therefore memory purchased — inference is majority memory-bound, on the order of ~70–90%; by raw token count it leans compute (prefill) because production is input-heavy, but those tokens are individually ~300× cheaper. The mechanism and crossover are anchored; the exact percentages are an estimate — the aggregate input:output distribution across all providers is not publicly disclosed. Sources: Towards Data Science, buildmvpfast, Medium (Chen; Patel), HuggingFace, arXiv 2512.22066, Silicon Data, iternal.ai, onprem.ai, Grizzly Peak, Mobisoft; plus the roofline anchors cited above. Estimate, not a measurement — not investment advice.
| Accelerator | HBM | BW / GPU | ~BW / MW | rel. decode TPS/MW |
|---|---|---|---|---|
| H100 | HBM3 | 3.35 TB/s | ~2.4 PB/s | 0.55× |
| H200 | HBM3e | 4.8 TB/s | ~3.4 PB/s | 0.8× |
| B200 · GB200 | HBM3e | 8 TB/s | ~4.4 PB/s | 1.0× (ref) |
| B300 · GB300 | HBM3e | 8 TB/s | ~3.9 PB/s | ~0.9× |
| Rubin · VR200 | HBM4 | 22 TB/s | ~7.5 PB/s | ~1.7× |
| Rubin Ultra | HBM4e | (2027) | higher | >2× |
Why bandwidth is the tokens/sec lever, and how these are built. The mechanism [established]: most production inference is memory-bandwidth-bound — generating each token requires reading the model’s weight parameters out of HBM, and the compute to process them takes less time than the read, so adding FLOPS without proportional bandwidth yields diminishing returns. In that regime decode tokens/sec is set by how fast weights (and KV) stream from memory, so it scales ~linearly with bandwidth: the H100→H200 step lifted bandwidth 1.43× (3.35→4.8 TB/s) and produced almost exactly 1.4× tokens/sec on the same model. Per-GPU bandwidth by generation [anchored]: H100 is 3.35 TB/s on HBM3, H200 4.8 TB/s and B200 8 TB/s on HBM3e, and Rubin (R100) reaches up to 22 TB/s on HBM4; B300/GB300 holds at 8 TB/s HBM3e (288 GB, 1,400 W) — capacity and FP4 compute rise, per-chip bandwidth does not. A Rubin NVL72 rack aggregates 1.6 PB/s across 20.7 TB of HBM4, and NVIDIA states the Rubin GPU nearly triples memory bandwidth compared to Blackwell. The HBM generation is the engine [anchored]: HBM4 delivers ~2 TB/s per stack versus HBM3e’s ~1.2, via a doubled 2,048-bit interface, yet bandwidth still grows only ~1.6× every two years while FLOPS scale ~3× — widening the memory wall; HBM4’s per-stack uplift is roughly +75–120%. Rubin Ultra (H2 2027) moves to HBM4e with 1 TB per GPU in 600 kW NVL576 racks. Per-MW conversion [modeled]: bandwidth/MW = (GPUs/MW) × (BW/GPU), with GPUs/MW from all-in power at a liquid-cooled PUE ~1.15 (~714 H100/H200, ~546 B200, ~490 GB300, ~340 Rubin per MW). The per-MW gain trails the per-chip gain because power climbs each generation — Rubin draws ~1,800–2,300 W per GPU versus Blackwell’s 1,000 — so HBM4’s 2.75× per-chip bandwidth lands at ~1.7× per MW. Why it’s the thesis: a megawatt’s token output is gated by HBM bandwidth, and the only way to raise it is the next HBM generation — supplied by exactly three firms, SK Hynix (~62%), Micron (~21%) and Samsung (~17%), with capacity sold out. That is the memory supercycle in one line: tokens/sec per watt is an HBM-bandwidth story (see §05·C·G). All MODELED: per-GPU bandwidths and the H200 scaling point are anchored to published specs; per-MW figures fold in power/PUE assumptions and a representative weight-streaming model, none of which is a single number. Estimate, not a measurement — not investment advice.
Provenance & the honesty line. Measured / cited anchors: decode is memory-bandwidth-bound, prefill is compute-bound (arXiv 2601.11822 and standard serving literature); a 70B FP16 model reads ~140 GB from memory per generated token, and on an H100's 3.35 TB/s that sets a ~42 ms/token floor ≈ ~24 tok/s regardless of FLOPS; H200 ≈ 34, B200 ≈ 57 on the same model (GMI Cloud, Spheron — B200 figures trace to GTC-2024 disclosures/estimates); the H100 pairs 1,979 FP8 TFLOPS with 3.35 TB/s — a 591:1 compute-to-memory ratio (Introl); measured MFU stays below ~20% at batch sizes under ~100 on H100 / Llama-3-70B, explicitly because VRAM cannot hold the KV cache needed for larger batches (arXiv 2405.01814 — the single best empirical statement of this section's thesis); one profiled inference kernel ran at 23% compute and 47% memory-bandwidth utilization (arXiv 2504.06319); H100s have been measured using only ~32% of peak memory bandwidth in distributed decode, with HBM accesses alone 30–50% of energy (arXiv 2602.18568); even large-batch serving stays DRAM-bound with significant compute idle (arXiv 2503.08311). The H200 proof point [NVIDIA product brief via GMI]: H100 and H200 share identical FP16 (989) and FP8 (1,979) TFLOPS; the H200's up-to-1.9× Llama-2-70B inference speedup comes entirely from memory (141 GB HBM3E @ 4.8 TB/s vs 80 GB HBM3 @ 3.35). KV-cache formula per request: 2 × layers × KV-heads × head-dim × seq-len × bytes (GMI). Derived [formula shown, labeled]: the chart's utilization curves are roofline ceilings — util ≈ min(100%, BW×B/peak) with FP16-dense peaks (H100/H200 989 TFLOPS, B200 ~2,250 est.) — real kernels achieve less (see the measured 23%/47% figures), so the idle problem is worse than the curves, not better. Illustrative [assumptions stated]: the capacity cut-offs assume a 70B-class model, FP8 weights ≈70 GB, FP8 KV ≈160 KB/token, 8K average context → ≈1.3 GB per request; real deployments shard across GPUs, page KV (vLLM-style), quantize, and disaggregate prefill/decode, so exact caps vary widely — the mechanism (capacity caps concurrency, concurrency drives utilization) is the anchored claim, not the specific integers. Prompt-verdict table [derived — reference math shown]: per-token costs on the section's reference config (70B FP16, H100, batch 1): prefill ≈ 2×70B FLOPs ÷ 989 TFLOPS ≈ 0.14 ms per input token (compute-limited); decode ≈ 140 GB ÷ 3.35 TB/s ≈ 41.8 ms per output token (bandwidth-limited) — the agent row adds the 200K-context KV read (~64 GB at GQA-class 320 KB/token) → ~61 ms/token. The crossover ratio (input tokens per output token at which prefill time equals decode time) is decode÷prefill ≈ 295 — algebraically identical to the ridge batch, since both reduce to peak ÷ (bandwidth × FLOPs-per-byte). Caveats: verdicts are per-request at batch 1 — production batching divides the weight-read share of decode by ~B until context/KV dominates, pulling crossovers down; prefill is idealized at 100% MFU (real prefill runs ~40–70%, which lengthens prefill's time share but doesn't change which resource limits each phase); token counts are illustrative (~4 chars/token; thinking budgets vary widely); prompt caching converts recomputed prefill into stored KV — trading compute time for HBM capacity occupancy, the section's thesis in miniature. Coverage note for the sixteen-row table: the shapes span the categories that dominate public usage analyses — coding/agentic work (the largest API category), chat, writing/rewriting, reasoning, RAG & support, summarization, translation, extraction/classification, research, and vision — with illustrative token counts, not measured shares (platform mixes vary; one image counts ≈ 1.5K prefill tokens). Methodology consistency: rows whose decode runs at long context (the 10-K, agent turn, agentic-coding loop, deep research, needle-in-haystack) include the per-token KV read in the decode cost; the offline-classification row is the one deliberate exception to batch-1 — scored at batch 256 to demonstrate the flip that production batching produces. Frontier scenario [modeled — every workload number is an assumption]: Anthropic publishes no architecture details for Claude Fable 5 (the model that drafted this dashboard does not know its own parameter count — it isn't disclosed even to it), so the scenario uses round frontier-class figures in line with widely-reported analyst estimates of GPT-4-class systems (~1.8T-parameter MoE): ~2T total / ~120B active, NVFP4 weights (~1 TB, sharded ~14 GB/GPU across an NVL72-class pod), KV ≈250 KB/token with GQA/MLA-style compression; Claude's 200K context window is the one public spec used. Utilization here = decode-phase ceiling vs dense-FP4 peak: at short context, batching amortizes weight reads and the ceiling ≈ min(compute ridge, KV asymptote); at 200K the KV read per token (~50 GB/request) dominates and the ceiling collapses to ~0.3–0.6% regardless of batch — added capacity then buys concurrency (how many 200K requests fit), not utilization. MoE routing makes real ceilings lower still (large batches touch most experts, weakening amortization), prefill mixing raises blended MFU, and production kernels run below all of these ceilings (see the measured anchors above). Frontier GPU specs [published / reported]: B200 192 GB HBM3E · 8 TB/s · 9 PF dense FP4 (shipping); B300 288 GB (12-Hi HBM3E) · same 8 TB/s · 15 PF dense FP4 — its advantage is "purely about fitting larger models or longer contexts… rather than serving each token faster" (Spheron; SemiAnalysis; Tom's Hardware; IntuitionLabs; shipping since H2'25); Vera Rubin 288 GB HBM4 · 50 PF dense FP4 · bandwidth reported at 22 TB/s in the latest GTC-2026 coverage after evolving 13 → 20.5 → 22 TB/s across reporting as NVIDIA pushed HBM4 pin speeds (tech-insider, SemiAnalysis, IntuitionLabs) — sampling Q4 2026, volume Q1 2027, so all Rubin figures are preliminary. Corroborating context from the same reporting: memory is set to consume ~30% of hyperscaler data-center spend this year (~4× 2023) and NVIDIA system memory costs are up ~485% (Tom's Hardware). Open-weights block [published architecture + derived math]: DeepSeek V4 Pro specs are from its Hugging Face model card / paper abstract (Apr 24 2026, MIT): 1.6T total / 49B active, 61 layers, hidden 7168, 384 routed + 1 shared experts (6 active/token), native 1M context; the abstract states the hybrid CSA+HCA attention needs 27% of single-token inference FLOPs and 10% of the KV cache vs V3.2 at 1M context. KV/token is derived from that ratio: V3.2's MLA cache ≈ 576 dims × 61 layers × 2 B ≈ 70 KB/token → V4 Pro ≈ 7 KB/token; cross-check: reporting puts it at ~2% of an 8-head GQA BF16 cache, and that GQA reference works out to ~250 KB/token — the same figure assumed in the closed-model scenario above, an independent validation of that assumption. Weights ≈1 TB mixed FP4/FP8, anchored to Lambda's note that the checkpoint fits on an 8×B200 node (≈14 GB/GPU sharded across an NVL72 pod). Directional caveat: the 1M-context bars model the per-token KV read as the full compressed cache — CSA/HCA's sparse reads touch less, so V4's true long-context ceilings sit above the bars shown (the conservative direction); capacity math uses full storage, which is correct regardless. "Largest and highest-performing" disclosure: GLM-5.2 (744B) and Kimi K2.6 / MiMo-V2.5-Pro (1T) edge V4 Pro on the Intelligence Index (≈54 vs 52), but V4 Pro is the largest open model, #1 on open agentic Elo, and highest open SWE-bench — the closest single fit; swapping the block to any of those is a config change. The meta-point the two blocks make together: the best open architecture is explicitly engineered around the memory wall (MoE sparsity + compressed/sparse attention) — demand-side adaptation to memory scarcity — and cheap 1M-token context is exactly what unlocks more long-context usage, so per-request memory efficiency feeds total memory demand rather than reducing it (sources: DeepSeek V4 model card, Latent Space/Lambda, Artificial Analysis, morphllm, aimadetools, codersera). On-thesis: this is the machine that converts token demand (§06·D) into memory demand (§05·B, §06·D·M) — and why TrendForce frames the supercycle as a "memory wall" problem: as AI shifts to inference, compute demand per token falls while memory demand rises, with inference set to be the primary AI-server driver by 2029. Sources: arXiv 2405.01814, 2504.06319, 2602.18568, 2503.08311, 2601.11822; GMI Cloud; Spheron; Introl; NVIDIA H100/H200 datasheets; TrendForce "Memory Wall" insight (Jan 2026). Not investment advice.
One map of every trend compounding memory demand — C = capacity (GB), B = bandwidth (TB/s). The point of seeing them together: these multiply, not add. Longer contexts × more reasoning tokens × more agents × more users × bigger models — each is a separate factor on the same HBM bill, which is why token volume can grow 24× while memory demand grows faster.
Two new demand/price signals were added: Meta started charging developers for a model API, while AWS raised Capacity Block prices effective Jul 1. Monetization is appearing, but so is the infrastructure scarcity premium.
| Trend | C / B | Scale of effect | Tracked in |
|---|---|---|---|
| Context windows — KV cache grows linearly with tokens in context | C + B | 128K ≈ 19 GB KV per sequence (GQA) vs ~0.9 GB (MLA); decode re-reads it every token | §06·D·W |
| Reasoning / thinking tokens — answers now include long hidden traces | B | 10–20× more output tokens per query; all decode = all bandwidth | §06·D·W agg. |
| Agentic loops — full context re-sent every tool step; agent teams run parallel instances | C + B | 0.4–2M tokens per task; per-dev use +18.6× in 9 months | §08·E |
| Model scale / MoE totals — all experts must be resident even if few activate | C | 1.6T-param checkpoint ≈ 1 TB in FP8 — a full NVL72 rack to hold one model | §06·D·W open block |
| Batch / concurrency — saturating compute needs KV for ~281 sequences at once | C | roofline batch × context × KV/token; 5.4 TB at 128K standard-KV | §06·D·W per-MW |
| Multimodality — images ~1.5K tokens each; video/audio are token streams | C + B | vision rows land memory-bound in both prompt tables | §06·D·W tables |
| Prompt caching — the fix that eats capacity: cached KV kept resident/tiered to DRAM | C | 90% input discount only exists because the KV is stored, not recomputed | §06·D·W · §01 |
| Token volume growth itself — more users, more queries, Jevons dynamics | C + B | Goldman: 24× enterprise tokens by 2030 (120 quadrillion/mo) | §08·E · §08·D |
| FLOPS outrunning bandwidth — compute grows ~3×/2yr, HBM BW ~1.6×/2yr | B | the wall widens each generation → bandwidth carries a structural premium | §06·D·W BW/MW · §05·C·G |
| On-device AI floors — edge inference raises minimum DRAM per phone/PC/car | C | iPhone base 8→12 GB; Tesla 300 GB+/vehicle trajectory | §08·C · §07·B·T |
| Multi-tenancy extras — LoRA adapters, draft models for speculative decoding, embeddings/RAG stores | C | each resident alongside weights; RAG shifts GB into server DRAM too | §01 · §06·D·M |
Label: SYNTHESIS. This section introduces no new figures — every number is sourced and cited in the section its row links to; this is the one-glance union. The compounding claim is the analytical content: demand drivers are multiplicative (context × reasoning × agents × users × model size), while supply-side relief is per-factor (MLA compresses KV ~20× but touches only one factor; HBM4 lifts bandwidth ~1.7× per MW but not capacity per user). The bear case is the same table read backwards: efficiency gains (compression, distillation, caching, smaller routed experts) attack individual rows — kill-switch #5 (§02·D) watches whether efficiency ever outruns compounding. It has not yet. Not investment advice.
Quarterly shipped capacity by memory/storage type, 2022 → 2030E, in billion gigabytes (Bn-GB) — numerically equal to exabytes (EB). The tiers differ by orders of magnitude (HDD ships ~10× the bytes of all DRAM), so they're split into two charts: compute / active memory below, then storage media beneath it — otherwise HBM would be an invisible sliver next to nearline HDD. This is an industry model, not audited company-reported shipment data.
Micron’s first Idaho fab now targets first wafer in mid-2027, the second in late-2028; New York vertical construction began ahead of schedule. These dates strengthen the model’s point that large new bit supply cannot relieve 2026.
Scale anchors (real): HDD shipped ~900 EB in 2023 and ~250–300 EB/quarter (Coughlin/Nidec); SSD ~90 EB in Q1 2024, roughly 12× DRAM capacity and on par with total HDD bytes (Yole/Forward Insights); DRAM ~30 EB/quarter with HBM ~6% of DRAM bits (industry estimates); tape a small but growing archive tier. Forward quarters (2026Q3→2030Q4) extrapolate each tier's bit-growth CAGR — DRAM/HBM fastest, HDD steady, tape slow. These are modeled proportions calibrated to published scale relationships, not audited shipment reports. Quarterly splits use observed seasonality. Values are shipped capacity (supply), not installed base. 1 Bn-GB = 1 EB = 1 billion gigabytes. Sources: Yole Intelligence, Forward Insights, IDC, Coughlin Associates, TrendForce, company filings. Not investment advice.
A section per maker: past and projected capital expenditure, and a model translating that capex into estimated new memory supply by type. The logic is the industry's own: capex buys wafer-fab equipment and cleanroom; at a known capital intensity (dollars per EB of annual bit capacity) that yields new bits — but with a 6–8 quarter lag, which is exactly why 2025–26's record spend doesn't relieve the shortage until 2027–28.
Micron’s long-range U.S. plan is now more than $250B through 2035, up from $200B. The chart’s near-term annual capex series is unchanged until a new fiscal guide is filed, but the strategic supply pipeline and fab dates are updated.
Summing the per-company models: estimated net new annual bit supply coming online each year (lagged from capex), by type. This is the supply side of the bit-gap — the wave that closes the shortage in 2027–28.
CapEx anchors (real, from filings & TrendForce): Micron FY22 $12.0B → FY23 ~$7.0B (cut ~40% in the downturn) → FY24 ~$8.1B → FY25 ~$13.8B → FY26 ~$27B (revised sharply up; $7.1B in FQ3 alone per the Jun 24 FQ3 report), with further increases planned for FY27; >$250B U.S. investment plan through 2035 (Idaho greenfield output now expected calendar 2028). SK Hynix ~$12.5B (2024) → ~$21B (2025, +30% on HBM) → ~$20.5B (2026E); M15X output begins 2H 2026, Yongin cluster from 2027. Samsung ~$18B → $20B (2026E); P4L expansion. Industry DRAM capex $53.7B (2025) → $61.3B (2026, +14%); NAND $21.1B → $22.2B. The capex figures are well-sourced; the capex→supply translation is a model. Capital intensity is blended and approximate, lag is a simplification (real fab ramps are gradual, not a step), and "efficiency" bundles yield, node mix, and maintenance-vs-growth capex into one factor. Directionally sound — the supply wave is real and lands 2027–28 — but the EB figures are estimates, not forecasts. Sources: company 10-Ks/8-Ks, TrendForce, The Elec, Coughlin Associates. Not investment advice.
The demand-side mirror of the capex spend: Remaining Performance Obligations (RPO) — contracted-but-not-yet-recognized cloud revenue, the most forward-looking disclosure these companies make. In 2026 the four big clouds — Microsoft, Oracle, Google, Amazon — collectively carry over $2 trillion in backlog, up from a few hundred billion a year earlier, as AI mega-deals (OpenAI's Stargate, Anthropic's multi-cloud pacts) landed in the books. This is the contracted demand that, in turn, drives the memory orders. Honesty note: RPO became a standardized disclosure only after the ASC 606 accounting standard (~2018), so a true 10-year history doesn't exist for the early years — those are shown as sparse / not-comparable, not invented.
Latest filed RPO values remain the valid anchors. The next major refresh begins with Alphabet on Jul 22, followed by Microsoft, Meta and Amazon; no pre-earnings estimate has been inserted as an actual.
Customer split is from The Information's May 21 2026 snapshot; Oracle's bar adds a hatched $85B segment for contracts landed after the snapshot, so bar lengths match each firm's latest reported total (Oracle $638B by May 31) rather than misleadingly drawing the current leader shortest.
Provenance & the honesty line. RPO/backlog [anchored — company 10-Q/10-K & earnings, quarterly]: Microsoft commercial RPO (FYE Jun): $141B (Jun'21) → $189B (Jun'22) → ~$224B (Jun'23) → ~$269B (Jun'24) → ~$315B (Mar'25) → $368B (Jun'25) → $398B (Sep'25) → $625B (Dec'25, +110% YoY) → $627B (Mar'26, +99%); ~45% now OpenAI-attributed, balance boosted by Anthropic (Microsoft 8-K/IR, Constellation). Correction from a prior build: an earlier version showed Microsoft ~$112B for 2023 — that was the cloud-only RPO subset; total commercial RPO was ~$224B then. Now fixed. Oracle RPO (FYE May): ~$44B (FY21) → $65B (Dec'22) → $80B (Feb'24) → $98B (May'24) → $99B (Sep'24) → ~$138B (May'25) → $455B (Sep'25, +359% YoY) → $523B (Dec'25, +433%) → $553B (Feb'26) → $638B (May'26, +363% YoY, up $85B sequentially) — the $300B OpenAI/Stargate deal is the anchor (Oracle 8-K/IR, DCD, Cloud Wars). Google Cloud backlog (disclosed from ~2022): ~$52B ('23) → ~$92B (Mar'25) → "nearly doubling quarter on quarter to over $460 billion" (Sundar Pichai, Alphabet Q1 2026 8-K). AWS RPO (cited from ~2022): ~$105B ('23) → $189B (Mar'25, +20%) → $364B (Mar'26, +93% YoY), excluding a new $100B OpenAI commitment on top of an existing $38B contract (Amazon IR, Global Data Center Hub, Cloud Wars). Current-snapshot decomposition [The Information, May 21 2026]: Microsoft $280B OpenAI + $30B Anthropic + $317B other ≈ $627B; Oracle $300B OpenAI + $253B other ≈ $553B; Google $200B Anthropic + $268B other ≈ $468B; Amazon $138B OpenAI + $100B Anthropic + $226B other ≈ $464B (per the reference chart; The Information / JPMAM). The honesty caveats: (1) RPO standardized disclosure dates to ASC 606 (~2018) — pre-2019 figures are sparse / not comparable and are drawn faint, not fabricated. (2) Fiscal calendars differ (Oracle FY ends May 31; Microsoft Jun 30; Amazon/Alphabet Dec 31) — the time axis is approximate calendar-aligned. (3) RPO is contracted revenue, not guaranteed cash — concentration in a few AI customers (OpenAI ~45% of MSFT's, $300B of Oracle's) is real counterparty risk, and skeptics question whether OpenAI can honor ~$60B/yr commitments. (4) The customer decomposition is reporting-derived (The Information), not a GAAP line item. Modeled: the connecting curves between anchored quarters. Sources: company 10-Q/10-K & earnings calls, The Information, JPMAM, DCD, Sherwood, Constellation, Cloud Wars, Global Data Center Hub. Not investment advice.
The RPO section above shows the money; this shows the electricity — publicly disclosed compute commitments by the two frontier labs, in gigawatts. Power is the constraint upstream of everything in this dashboard: a gigawatt committed is land, transformers, accelerators, and — the reason it's here — a fixed ratio of HBM and DRAM that must be manufactured. As of the June 2026 compile, OpenAI has ~18.75 GW committed across Stargate/Oracle, AMD, AWS and Cerebras, and Anthropic ~12.8 GW across AWS, two Google structures and SpaceX — of which ~10.8 GW was added in April–June 2026 alone.
No newly signed, quantified GW contract superseded the June compile. Announced commitments remain distinct from deployed power draw; the section’s accounting convention is unchanged.
Provenance. Commitment figures are a point-in-time June 2026 compile (The Product Compass / TheWhiteBox Consulting / JPMAM) of publicly announced deals: OpenAI — Stargate with Oracle 10 GW, AMD MI450 6 GW, AWS 2 GW, Cerebras 0.75 GW (≈18.75 GW); Anthropic — AWS 5 GW, Google + Broadcom 3.5 GW, Google 2 GW, SpaceX 0.3 GW atop a ~2 GW pre-April base (≈12.8 GW, ~10.8 GW of it added April–June 2026). Caveats: commitments ≠ deployed draw — these are multi-year build-outs; announced GW definitions vary (IT load vs facility); the compile predates any July deals; and the memory bridge is labeled illustrative with its per-GPU wattage and 192 GB assumptions shown. Not investment advice.
The memory-side mirror of the hyperscaler backlogs above: with FQ3 (Jun 24), Micron began disclosing remaining performance obligations under a new regime of 16 take-or-pay Strategic Customer Agreements running 2026 through end-2030. Reported RPO at quarter-end was >$5B — but that counts only agreements executed by May 28; including the SCAs signed just after, RPO is ≈ $100B, with 14 of 16 agreements entering the FQ4 reporting. The construction is deliberately conservative: minimum committed volumes at floor pricing (Micron expects revenue to "well exceed" RPO), with price ceilings set at CQ2-2026 levels — which is also a cap worth remembering.
Micron’s Jun 24 RPO/SCA figures remain the latest contract data. The Jul 9 >$250B U.S. investment announcement is added as execution context, not mixed into RPO.
The FCF trap, flagged: the $18B of cash deposits is not prepaid revenue — it flows through financing cash flow and is returned over the back half of each agreement. Adding it to FQ3's record $18.3B adjusted FCF double-counts; this dashboard doesn't. Near-term revenue from the FQ3-closed agreements is small (~$1.8B next 12 months — early automotive deals); the $100B substance arrives with the FQ4 10-K. Read against §06·F·B: cloud buyers now carry ~$2.2T of committed demand, and the memory supplier they depend on has, for the first time, ~$100B of committed supply — floor-priced, ceiling-capped, and deposit-backed. Calendar: Jul 10 2026 — SK Hynix ADR begins U.S. trading; Dec 9 2026 — CHIPS-grant two-year mark unlocks Micron's shift toward returning ~100% of excess cash.
Provenance. All figures from Micron's FQ3-2026 prepared remarks, 8-K press release, 10-Q and earnings call (Jun 24–25 2026): RPO >$5B as reported / ≈$100B including SCAs executed after quarter-end (14 of 16 in FQ4 reporting); 16 take-or-pay SCAs, generally 2026–2030; ~20% of DRAM and ~30% of NAND capacity committed (sources range 30–33% on NAND); $22B of deposits and financial commitments ($18B cash, ~$4B LCs), >$400M received in FQ3 and ~$10B expected in FQ4, returned in the back half of each agreement via financing cash flow; RPO built on minimum volumes at floor prices with ceilings at CQ2-2026 levels, revenue expected to "well exceed" RPO; next-12-month revenue on FQ3-executed agreements ≈$1.8B. Honesty notes: this is the first print of a brand-new disclosure — definitions will firm up in the 10-K; Micron's RPO (floor-priced minimum volumes) is not directly comparable to cloud RPO (contracted service revenue), so the §06·F·B mirror is a framing, not an equivalence. Not investment advice.
What it costs to rent an AI accelerator by the hour is one of the cleanest real-time reads on accelerator supply/demand — and that same tightness is what pulls HBM and memory demand through the whole chain on this page. When GPUs are scarce, rental rates spike; when capacity floods in, they fall. Embedded below is Ornn's Compute Index, a live tracker of historical GPU rental price indices (H100, H200, B200, A100, RTX 5090).
The third-party rental panel remains a live external source. The local fallback was rechecked Jul 12; no synthetic spot price was substituted when the iframe cannot load.
This panel embeds a third-party live website — Ornn's Compute Index (ornn.com) — not data compiled by this dashboard. Its figures, methodology, coverage and uptime are entirely outside our control, and the embed may not render in every context (the Claude artifact sandbox blocks external frames, and a provider can disallow being framed via response headers); a direct link is provided as a fallback. Why it matters here: GPU rental rates are a fast, market-set proxy for accelerator scarcity — sustained high rates signal tight supply (bullish for the memory makers feeding those accelerators), falling rates can foreshadow a demand cooloff. Rental pricing reflects many factors beyond memory (compute supply, financing, power, contract vs spot), so treat it as one signal among the others on this page, not a direct memory-price gauge. Source: Ornn (dashboard.ornnai.com). Not investment advice.
A rare public, market-clearing price for the AI compute that drives memory demand. EC2 Capacity Blocks for ML reserve NVIDIA GPU clusters for fixed windows, and AWS says reservation fees are updated with supply and demand. The rates below use the Jul 1, 2026 schedule now in effect. The history separates on-demand pricing from Capacity Blocks because the two products move on different schedules. Source: aws.amazon.com/ec2/capacityblocks/pricing.
The table now treats the Jul 1 prices as current: B300 $14.04, B200 $12.355, U.S. H100 $5.191, H200 P5e $5.97 and U.S. P5en $6.865 per accelerator-hour.
Provenance. Current Jul 1, 2026 AWS effective rates per accelerator-hour: P6-B300 $14.04; P6-B200 $12.355; P5 H100 $5.191 in U.S. regions ($4.72 non-U.S.); P5e H200 $5.97; P5en H200 $6.865 U.S. ($6.241 non-U.S.); P4de A100 $2.214 U.S. Other listed products were unchanged. Prior rates are retained in the comparison column. Capacity Blocks are sold as fixed reservations and vary by region; the historical connecting curves remain interpolations where AWS does not publish a daily series. Source of record: AWS Capacity Blocks pricing page, checked Jul 12, 2026. Not investment advice.
Below the chips, AI's data exhaust drives the other half of the supercycle: enterprise SSDs for hot data and a hard-drive oligopoly for the cold tier. Both are sold out.
No newer audited exabyte shipment set replaced the current HDD/SSD anchors. July memory and cloud-pricing news strengthens the storage scarcity narrative but does not justify rewriting historical capacity.
Source: TrendForce Q4 2025 (approx.) · SK Hynix incl. Solidigm
The flash field is a layer race. Kioxia and SanDisk — allied for 25+ years across the Yokkaichi and Kitakami fabs even after SanDisk's spinoff — co-developed BiCS FLASH and are pushing past 300 layers in 2026. Enterprise SSD demand is the swing factor: SK Hynix's NAND revenue jumped ~48% in a single quarter on it.
From 200+ makers in the 1980s to three today. Nearline drives are ~90% of industry exabytes, and both WD and Seagate have sold out 2026 with agreements into 2028 — sending consumer drive prices up ~50% in five months. HDDs still win on cost-per-terabyte, so AI's cold data keeps the platters spinning.
The supercycle isn't only a datacenter story. AI is pushing memory into physical machines — and the standout is the self-driving car, which can carry more memory than a server. A robotaxi fuses lidar, radar and camera feeds in real time, runs neural nets on-board, logs everything for safety, and duplicates it all for redundancy. Robots and AR/VR add to the pull. None of this rivals datacenter volume yet, but it's the fastest-growing new demand — and, like phones, it's already feeling the squeeze (Meta raised Quest prices ~20% on the memory crunch).
Tesla expanded robotaxi service to Miami, its fourth city, but the fleet remains small and geofenced. The edge-memory thesis is intact; deployment scale is still far below the dashboard’s long-range scenario bands.
Estimated DRAM + NAND shipped into these three categories per year, in exabytes. Automotive dominates — it's the only one at real scale today — but robotics is the steepest curve on a tiny base. Switch between viewing the stack by category or by memory type (DRAM vs NAND). Solid = historical estimate; hatched = projection.
Edge memory is a modeled estimate (units × per-device memory content), and the three legs differ sharply in reliability. The DRAM/NAND split is itself an assumed ratio, not a separately-sourced series: by capacity (bits), storage dominates, so NAND is taken at ~86–93% of automotive and AR/VR content (rising slightly over time as autonomy/logging grows) and ~65–72% for robotics (which is more DRAM/HBM-weighted because real-time inference is bandwidth-bound). DRAM is far smaller in bits but higher-value per bit, so its revenue share is much larger than its capacity share shown here. A third type — NOR flash (boot code/firmware in ECUs) — is real in automotive but tiny by capacity and isn't charted separately. Automotive is the most solid leg: per-car content ~90GB (2023) → ~278GB (2026) rising toward 2–4TB on high-end/autonomous vehicles by 2030 (Micron); L1/L2 ≈ 8GB e-MMC, L3 ≈ 128–256GB, L5 > 2TB (TrendForce); ADAS+AD ≈ 40–45% of automotive memory revenue; ~3M fully-autonomous and 15M+ L2+/L3 vehicles expected by 2030, on a base of ~85M cars built/yr. AR/VR is moderate: shipments ~9.6M (2024) → ~37M by 2030 (TrendForce, ~23% CAGR), per-device memory 8–16GB (Quest 3 8GB, Vision Pro 16GB); already memory-constrained (Meta +~20% Quest pricing, Sony cut PSVR2). Humanoid robotics is the softest forecast in this entire dashboard — barely any units ship today (~500 in 2025; Tesla admits no Optimus does "useful work" yet), and 2030 estimates range from ~100K (Robotomated) to 1.2M (BofA) to Musk's "millions," with per-robot memory a guess; treat that layer as scenario, not forecast. Exabytes = billion GB. Sources: Micron, TrendForce, IDC, Verified/PS Market Research, BofA, company specs & disclosures. Not investment advice.
The companion dataset to the "memory monster" ladder above (§07·B) — and the honest picture is starker than most coverage suggests: every consumer Tesla ever delivered is SAE Level 2. Autopilot and FSD (Supervised) require active driver supervision — Tesla's own filings say so verbatim — so owning the FSD package (1.28M cumulative holders) does not change a car's SAE level. L4 exists only in the unsupervised Robotaxi operation (live across the Austin metro plus two more Texas cities) and the Cybercab, which entered volume production in 1H 2026 with no steering wheel or pedals. Tesla holds no L3 certification anywhere and its stated architecture skips L3 entirely; L5 does not exist for any maker. The chart shows what that means in units: six solid years of L2, an L4 sliver appearing in 2026, and a modeled fan to 2035. Update (Jul 2): Q2 deliveries came in at 480,126 — a 25% YoY jump that smashed the ~406K consensus by ~74K and broke a two-year decline streak. Crucially, every one of those 480,126 is still L2 — a record quarter changes the bar height, not the autonomy split.
Q2 deliveries remain 480,126. The autonomy overlay now notes Miami service and continued limited L4 fleet size; consumer-delivered Teslas remain SAE Level 2 despite FSD branding.
Provenance & the honesty line. Deliveries [anchored — company-reported]: 499,550 (2020) → 936,172 (2021) → 1,313,851 (2022) → 1,808,581 (2023) → 1,789,226 (2024, first annual decline) → 1,636,129 (2025, revised figure per the 10-K filed Jan 2026) → Q1 2026: 358,000+ delivered (+6.3% YoY; 408,000+ produced). Q2 2026: 480,126 delivered / 451,758 produced (Tesla 8-K, Jul 2) — up 25% YoY and 34% QoQ, ~74K above the 406,024 consensus (bullish estimates topped out ~418–420K), Tesla’s best-ever Q2 and first YoY growth since the 2023 peak; deliveries ran ~28K above production, working down Q1 inventory; Model 3/Y were 467,762 (97%), Other Models 12,364; 13.5 GWh energy storage deployed. H1 2026 = ~838K (358,023 + 480,126); full financials July 22. Note the split is unchanged by the beat — all 480,126 remain L2. FY26 tracking above the old ~1.65M consensus on this run-rate (Tesla 8-K/IR, SQ Magazine compile, Tesla Oracle, TechTimes). The L-split [definitional, not estimated]: an SAE level is a property of the system's design and certification, so the historical split is a matter of record rather than modeling: every consumer Tesla ships as L2 — Tesla's own investor materials footnote FSD (Supervised) with "Active driver supervision required; does not make the vehicle autonomous." The 1.28M cumulative FSD-package holders (Q1 2026) are therefore still L2 — owning the software ≠ a higher SAE level, a conflation this chart deliberately rejects. L4 [operational, small, partly modeled]: the unsupervised Robotaxi service is live (Austin metro + two additional Texas cities, priced under Waymo; paid Robotaxi miles roughly doubled sequentially in Q1 2026); the 2025 fleet was low-thousands of converted Model Ys (shown as ~0 at chart scale); Cybercab volume production commenced 1H 2026 per Tesla's Q4'25 and Q1'26 letters, but Tesla doesn't yet break Cybercab out of "Other models" (16,130 in Q1'26, which also holds S/X runout and Cybertruck) — so the ~30K L4 modeled for 2026 is an estimate, flagged. Projection [modeled — one mid path; the spread is enormous]: assumes an affordable-model-led L2 recovery, Cybercab becoming "the largest volume vehicle in the fleet over time" (Tesla's own Q1'26 language), and consumer unsupervised operation arriving late-decade in permitted regions only. Brackets: the Musk-scale case (2025 CEO award tranches: 20M vehicles, 1M Robotaxis in commercial operation, 10M FSD subscriptions) vs the analyst-flat case (~1.65M/yr persisting). Musk's autonomy-timing record — unsupervised driving promised repeatedly since 2016 — argues for discounting the top bracket, and this path sits well below it. If regulators force an L3-like intermediate for consumer unsupervised driving, some late-decade volume would route through L3; the chart follows Tesla's stated skip-L3 architecture. Memory bridge [illustrative]: per-level DRAM content and the Micron 300 GB+ L2+ anchor live in §07·B; the exabyte figure here is shipments × content arithmetic, not a demand forecast. The chart’s DRAM line uses these stated per-vehicle curves (GB, fleet-average new-build): L2 10 (2020) → 15 (’22) → 30 (HW4, ’23) → 60 (’25) → 120 (AI5 era begins, ’26) → 320 (’30) → 500 (’35), approaching Micron’s 300 GB+ L2+ figure late-decade as the mix upshifts; L4 ≈ 2× the consumer figure (600 → 1,100 GB) for redundant AI5-class computers and sensor buffering. Every point on that line is assumption × assumption — it is drawn to show shape (content growth dominating unit growth), not to forecast exabytes. Sources: Tesla 10-K, 8-K quarterly delivery releases, Q1-2026 shareholder letter, SQ Magazine, Tesla Oracle, TechTimes (Goldman/Barclays/RBC previews), notateslaapp. Not investment advice.
A future memory-demand driver Micron is betting on directly. Each humanoid carries an on-board AI "brain" running vision-language-action models locally — and Micron's CEO says a humanoid will need ~10× the memory of a high-autonomy car (which itself exceeds 300GB DRAM by 2026). Today the market is tiny and pre-mass-production — ~13,000 units shipped worldwide in 2025 (Omdia) — but the maker field is crowded and forecasts run from Goldman's cautious 76k-by-2027 to Morgan Stanley's 1B+ by 2050. Honesty note: 2025 shipments are anchored; everything forward is a forecast, and the forecasts disagree by orders of magnitude. Per-robot memory is an estimate from the dominant compute platform, not a universal spec.
No newer industry-wide 2026 humanoid shipment census superseded the 2025 anchor. Forward units and per-robot memory remain scenarios, not reported sales.
Provenance & the honesty line. Shipments [anchored]: ~13,000 humanoids shipped worldwide in 2025, Chinese firms in the top five, Figure 7th, Tesla 9th (Omdia via CNBC); Unitree the volume leader at ~5,500 units 2025; Tesla built only "hundreds" (missed its 5,000 target, public sales not before end-2027 per Musk); UBTech ~1.4B yuan in 2025 orders; Figure 03 at ~1 robot/hour at BotQ. Forecasts [cited — and they diverge hugely]: Goldman baseline 76,000 units by 2027 (vs ~500k some market participants price in) and $38B market / ~1.4M units by 2035; Morgan Stanley China shipments 50,000 (2026) → 446,000 (2030, $15B China market), and globally 1B+ humanoids by 2050 / $5T ecosystem; the spread between forecasters (Goldman conservative vs MS aggressive vs bull cases) is 4–10×. Memory per robot [anchored platform spec + CEO estimate]: NVIDIA Jetson Thor = 128GB memory, 2,070 FP4 TFLOPS, the dominant humanoid compute (Agility, Boston Dynamics, Figure, Galbot adopters; TrendForce/NVIDIA); Jetson T4000 = 64GB; Micron CEO Sanjay Mehrotra (Jun 2026): humanoids will need ~10× the memory of L2+ vehicles, which exceed 300GB DRAM/vehicle by 2026 — a "multi-decade demand cycle" (cryptobriefing/Micron). The honest caveats: (1) 2025 is the only solidly-anchored year; every forward point is a forecast and forecasters disagree by orders of magnitude — the chart shows three divergent scenarios rather than one false-precision line. (2) Near-term robot memory demand is negligible vs AI data centers — this is a long-duration option, not a 2026 catalyst. (3) Per-robot memory varies by tier (entry robots use far less than a Thor-class brain); the 128GB figure is the high-end platform, not an average. (4) The reference image's valuations/associations are point-in-time and some (e.g. 1X's $10bn target) are explicitly unverified. Modeled: the forecast curves between anchored points, and the scenario fan beyond 2025. Sources: Omdia (via CNBC), Goldman Sachs, Morgan Stanley, TrendForce, NVIDIA, Micron, The Product Compass / reference image, company disclosures. Not investment advice.
Samsung’s Q2 result confirms demand still exceeds effective supply, but cited Q2 ASP growth—DRAM +44%, NAND +53%—and the slower Q3 guide show the deficit is moving from acceleration toward peak tightness.
Source: PatSnap / JEDEC-tracked analysis, 2026
Supply can't keep pace; NAND growth is similarly capped near 17%. Downstream: Nvidia has reportedly cut gaming GPU output 30–40%, smartphone prices face 8–10% rises, and consumer hard drives are up ~50% — the AI buildout reaching into every device.
The clearest place the memory shortage shows up for ordinary buyers: Apple Mac delivery wait times. Because Macs use unified memory soldered on at build time, a DRAM squeeze hits them directly — and the wait scales with how much RAM you configure. This is the abstract supercycle made tangible: a consumer ordering a high-memory Mac in 2026 waits months, while the base model still ships same-day.
Apple’s late-June price changes—especially sharply higher high-memory upgrades—are added as a stronger observable symptom than lead times alone. Current shipping windows still vary by configuration and region.
Through 2026, Apple's online-store shipping estimates blew out specifically on high-memory configurations, while base models stayed quick. Reporting (MacRumors, Tom's Hardware, TrendForce) tied it directly to the AI memory crunch this dashboard tracks: Samsung and SK Hynix shifted capacity toward high-margin HBM/server memory, starving consumer DRAM. Apple removed the Mac Studio's 512 GB option entirely in March 2026, and demand from people building local-AI Mac clusters (the "OpenClaw" ordering frenzy) made it worse. Wait time has effectively become a real-time memory-scarcity gauge.
Modeled average delivery estimate across a representative basket of Mac configurations (base through high-memory), in weeks. The shape is the story: waits were normal (days) right through 2024 and most of 2025 — then the AI memory shortage hit in early 2026 and they spiked. This isn't a chronic Apple problem; it's a 2026 memory-supply event.
Wait times are configuration-specific snapshots from dated press reports, not a live per-model feed — Apple doesn't publish lead-time data, and its store estimates change daily and vary by region and channel. Anchors (US online store unless noted): Mac mini M4 Pro/64 GB = 16–18 weeks; base M4/16 GB ≈ 4 weeks; 512 GB M4 backordered into June (MacRumors, TrendForce, Apr–May 2026). Mac Studio M3 Ultra/256 GB = 16–20 weeks (4–5 months); 512 GB option removed from sale Mar 2026; in-store pickup pushed to September. MacBook Pro M4 Max/128 GB ≈ 5 weeks (early-2026 reporting), 36–48 GB a few weeks, base configs days. MacBook Air / iMac base ≈ same-day. Bars show the approximate midpoint of each reported window, scaled to ~20 weeks. The quarterly history is a modeled basket average, not a published series: 2024–2025 quarters reflect Apple's normal few-day lead times (no shortage reporting existed then); Q1 2026 is anchored to the Feb 2026 Mac Studio "14→54 day" reports (Tom's Hardware), and Q2 2026 to the Apr–May 2026 Mac mini/Studio blowout (MacRumors/TrendForce). The current quarter rechecks for the latest estimates on load when run inside Claude; opened as a file it shows the compiled value. The drivers — AI capacity diverting DRAM, plus local-AI Mac-cluster demand — are well documented; exact weeks for any given config today will differ. Sources: MacRumors, Tom's Hardware, Tom's Guide, TrendForce, BigGo, Cybernews. Not investment advice.
A different lens on the same demand: how much memory ships inside Apple devices sold each year, by type, 2010 → 2030. Apple alone consumes a meaningful slice of world memory, and the total has exploded — not mainly because Apple sells more units (iPhone volumes plateaued years ago), but because each device carries far more memory: storage has gone from 16 GB to 256 GB–1 TB, and RAM from 512 MB to 8–12 GB as on-device AI (Apple Intelligence) pushes it up. NAND storage dwarfs DRAM, so it's shown on its own axis context in the tooltip. Update (Jun–Jul 2026): the model's demand-side thesis just went from inference to confirmed fact — Tim Cook told the WSJ that memory costs have become unsustainable, called the squeeze a “hundred-year flood,” and confirmed iPhone price increases; Apple already raised Mac prices $100–500 (and iPad/Apple TV/HomePod) in late June. And in the middle of it: Cook is outgoing — hardware chief John Ternus becomes CEO September 1, a week before the iPhone 18 launch.
Apple’s memory-cost pass-through is now visible in product pricing, and reporting points to further high-end iPhone increases later in 2026. The unit/content model is unchanged until new shipment or configuration data arrives.
This is a two-layer model, not reported data — Apple discloses neither unit shipments (it stopped in 2018) nor memory content. It multiplies estimated annual unit shipments per product line (iPhone, iPad, Mac, Watch, others) by an estimated capacity-weighted average of NAND storage and DRAM per device, each rising over time. Anchors: iPhone ~232M units (2024), record ~247M (2025, IDC); Macs ~22–25M/yr (~6.2M in Q2 2025, IDC/Canalys); iPad ~50M/yr. Capacity assumptions: iPhone average storage ~16 GB (2010) → ~256 GB (2026E), DRAM 0.5 GB → ~8 GB; Macs/iPads scaled higher. NAND outweighs DRAM by ~20–40× per device, so it dominates the stack. Projection to 2030 assumes low-single-digit unit growth and continued capacity step-ups (on-device AI lifting the DRAM floor — Apple Intelligence needs ≥8 GB) — IDC notes 2026 smartphone units actually dip ~1% on the memory shortage itself, even as ASPs hit records. Jul 2026 refresh — the cost shock, quantified [cited]: the TechInsights model (via WSJ) has the same 12 GB DRAM package going from about $39 in iPhone 17 Pro to about $145 in iPhone 18 Pro (+272%), with the 256 GB base NAND tier from ~$13 to a projected $51; estimated build cost rises from ~$582 to ~$726, implying ~$1,371 to hold margin on a $1,099 phone — i.e. roughly +$270 on the 18 Pro to preserve margins. Base-model hikes of $50–150 and up to $200 on Pro are the projected range; DRAM/NAND contract prices jumped 90–95% QoQ in Q1 2026. Procurement color: Samsung reportedly planned +60% on LPDDR5X, opened at +100% — and Apple accepted immediately in emergency procurement meetings. The DRAM-per-device floor is rising exactly as modeled: the iPhone 18 line carries 12 GB to power on-device Apple Intelligence, and DigiTimes reports even the base iPhone 18 moves 8→12 GB. On duration, the disagreement is surfaced, not resolved: Cook expects memory pricing to “return to reasonable levels,” while IDC calls the shift a “permanent reallocation” of capacity toward AI, and analyst timelines for relief run from Q4 2027 (Counterpoint) to 2028 (Intel’s Tan) to 2030 (Kearney); Cook even said “everything needs to be on the table” when asked about sourcing from Chinese memory suppliers. This section’s cross-links write themselves: Apple raising retail prices on memory costs is kill-switch #5’s demand-destruction mechanism operating in the wild (§02·D), and the affordability ceiling TrendForce cited for the 3Q26 contract-price deceleration (§03) is the same phenomenon from the supplier side. Treat the totals as order-of-magnitude with a wide band; the trend (memory-per-device, not unit count, drives the growth) is the robust takeaway. Sources: IDC, Canalys, Counterpoint, Apple teardowns (iFixit/TechInsights), company history. Not investment advice.
The demand under the demand. All the memory in this dashboard is ultimately paid for by the revenue the AI application layer throws off — so here is that layer's income, built from every annualized run-rate the two leading labs have disclosed, with Facebook's first revenue years overlaid by company age as a benchmark. The story the curves tell: the two labs have diverged — OpenAI flattened near a $24–25B run-rate (~$2B/month by its own account, user base plateaued ~900M weekly) while Anthropic, carried by Claude Code and enterprise API, climbed past $47B and is projected near $50B. Against Facebook at the same age, the gap is almost comic: two-plus years into earning revenue, Facebook made ~$48M/year — Anthropic is roughly 1,000× larger.
No newer audited OpenAI/Anthropic run-rate disclosure replaced the plotted anchors. Meta’s Jul 9 move to charge developers for model API access is added as a new app-layer monetization datapoint, outside the two-lab series.
Provenance & the honesty line. The metric: neither lab reports monthly revenue — both periodically disclose an annualized run-rate (latest month × 12). "Implied monthly" here is simply run-rate ÷ 12; it's a forward annualization, not trailing recognized revenue, so full-year GAAP totals run lower during fast growth. Anthropic [disclosed]: $87M run-rate (Jan 2024) → $1B (Dec 2024) → $4B (Jun 2025) → $9B (Dec 2025) → $14B (Series G, Feb 12 2026) → $19B (Mar) → $30B (Apr 7 company post) → $47B (Series H, mid-May, $965B valuation); ~$48.5–50B projected for Jun–Jul (VentureBeat revenue-walk, CNBC Series H, company disclosures). OpenAI [reported/blended]: ~$2B run-rate exit-2023 → $5.5B exit-2024 → $10B (Jun 2025, Reuters) → $20B (CFO, Jan 2026) → ~$25B (Feb–Mar) → ~$24B (Jun, "≈$2B/month" by its own account), apparently plateaued mid-2026 (Reuters, OpenAI funding post, TechnologyChecker Jul 3). Facebook overlay [actual, historical]: aligned by company age, not calendar — chart-2024 = FB-2004 (founded Feb 4 2004, first revenue $382K per its IPO S-1); plotted values are actual annual revenue ÷ 12 ($382K → $9M → $48M → $153M across 2004–07), no projection (TechCrunch/S-1). Filling gaps: dots are disclosed/actual; between two dots, exponential (constant-growth) interpolation; the dashed tip projects the labs' current month — Anthropic forward from mid-May $47B (nudged for reports of cooling token spend), OpenAI held near its stated ~$2B/month. Confidence & the dispute [surfaced, not buried]: Anthropic's figures are largely official fundraising disclosures; OpenAI's are blended and vary by method — and in April 2026 OpenAI publicly argued Anthropic's ~$30B figure was overstated by ~$8B, contending Anthropic books gross end-customer spend through AWS/Google/Azure while the net figure is closer to ~$22B; some trackers (Sacra) instead put OpenAI higher, near ~$33B. Treat every run-rate headline as directional, not audited. Why it's on-thesis: this app-layer revenue is what funds the compute commitments (§06·F·C), the hyperscaler backlogs (§06·F·B), and ultimately every bit of memory demand in this dashboard — the tokens that hit the memory wall (§06·D·W) are the same tokens being monetized here. Adapted from a user-supplied run-rate tracker; figures re-verified Jul 2026. Sources: CNBC, VentureBeat, Reuters, Epoch AI, Sacra, FutureSearch, TechCrunch/Facebook S-1, OpenAI & Anthropic disclosures. Run-rates are annualized public disclosures, not audited financials — not investment advice.
The demand side at maximum resolution: how many tokens does one employee burn per day? 2026 made this answerable — companies built literal internal leaderboards ("Claudeonomics" at Meta, "AI God" ranks at Sendbird), then the bills arrived and the same companies started dismantling them. The spread below runs five orders of magnitude, from ≥100M tokens/day power users to the median firm’s ~$11/employee/month — token demand is a power law, exactly like the app-layer revenue (§08·D) and capex (§06·F) it feeds.
Meta’s internal token-leaderboard episode has shifted from “use more” to budget control: reporting says the company is centralizing access and formalizing token budgets after usage put 2026 costs on a multi-billion-dollar trajectory.
| # | Who | Tokens / employee / day | $ signal | Label |
|---|---|---|---|---|
| 1 | Sendbird "AI God" engineers (5–10% of eng staff) | ≥100M | prizes, planned extra vacation days | reported |
| 2 | Heavy agentic developers, industry-wide (incl. Microsoft E+D pre-cancellation) | ~20–80M | $500–$2,000/mo bills | derived |
| 3 | Sendbird CEO (rank: "Custom Tool Builder") | 30M | 70% via Claude Code | reported |
| 4 | Meta — company-wide average, all ~85K employees | ~29M | "approaching billions" in 2026 | derived: 73.7T ÷ 85K ÷ 30d |
| 5 | Typical enterprise Claude Code developer | ~3–6M (active day) | $13/active day · $150–250/mo · 90% under $30/day | derived from reported $ |
| 6 | Uber engineers (95% monthly adoption, ~70% of committed code AI-generated) | capped | $1,500/mo/employee limit after budget gone in 4 months | reported |
| 7 | Aerospace & defense mfr power users | cap burned in 4 days | $250/mo limit · Opus + fast-mode disabled | reported |
| 8 | Top-1% firm on Ramp (per-employee median) | — | $7,450/employee/mo | reported |
| 9 | Top-10% firm on Ramp | — | $611/employee/mo | reported |
| 10 | Median firm on Ramp | — | $11.38/employee/mo | reported |
| 11 | US economy-wide (Atlanta Fed, anticipated 2026) | — | $2,068/employee/year (+50% YoY) | reported |
Sources, derivations & the honesty line. The two marquee numbers [cited]: Meta employees consumed 73.7 trillion tokens in roughly 30 days, tracked on an internal leaderboard called "Claudeonomics"; costs are approaching billions for 2026, and Meta is dismantling the board for a centralized "AI Gateway" with formal token budgets from 2027 — across all 85,000 ranked employees that derives to ~29M tokens per employee per day, an average that matches an AI-startup CEO’s personal burn. Sendbird ranks staff from "Beginner" to "AI God" — 100M+ tokens/day — with 5–10% of engineering at god tier, ~70% of it through Claude Code, and prizes for usage. The middle of the curve [cited]: enterprise Claude Code averages ~$13/developer/active day and $150–250/month, with 90% of users under $30 on any active day; agentic tasks consume 400K–2M tokens each, power users reach $500–$2,000/month, and per-developer consumption rose ~18.6× in nine months; Microsoft’s Experiences+Devices division ordered engineers off Claude Code by June 30 after ~$2,000/engineer/month exhausted the annual budget — moving to $39/seat Copilot, a 51× CFO math. The long tail [cited]: Ramp per-employee medians: $11.38 typical firm, $611 top decile, $7,450 top percentile — average company $140,842/mo vs median $2,246, a power-law distribution — and the Atlanta Fed anticipates $2,068 per employee for 2026, up 50%. The cultural whiplash, six months end to end: Meta, Amazon and Microsoft set internal token-usage targets in early 2026; by mid-year Amazon shut its leaderboard down ("Please don’t use AI just for the sake of using AI") and replaced counts with shipped-code metrics, Uber capped at $1,500/mo after burning its annual budget in four months, and a defense manufacturer’s $250 caps were burned through in four days; Meta’s CTO put the epitaph on tokenmaxxing: "All motion is not progress and token usage alone is not a measure of impact of any kind". Honesty notes: units are deliberately mixed — some rows disclose tokens, some only dollars, and $→token conversion varies ~100× with model choice and caching, so dollar rows are left in dollars rather than fake-converted; "derived" rows show their math; rankings compare unlike populations (one company’s elite vs another’s average). Why it’s on-thesis: these are the tokens that hit the memory wall (§06·D·W) and get monetized in §08·D — and the budget caps arriving mid-2026 are a live demand-quality read for kill-switch #5 (§02·D): Goldman still projects 24× enterprise token growth by 2030 (120 quadrillion/month), but the era of burning tokens as a KPI is visibly ending. Reported + derived snapshot, Jul 2026 — not investment advice.
As Korean and U.S. makers chase the high-margin top of the stack, China's CXMT and YMTC scale commodity memory into the gap — and race, under export controls, to build a domestic HBM supply chain for Huawei and other local AI players.
CXMT begins book-building Jul 15 for a 29.5B yuan ($4.34B) Shanghai IPO. New motherboard validation also pushes CXMT DDR5 modules to higher speeds, strengthening its commodity-DRAM position even as leading-edge HBM remains behind.
CXMT nearly tripled monthly DRAM wafer output to ~290k in two years and is migrating from DDR4 to DDR5. It filed a Shanghai STAR Market IPO (~$4.1B) and shipped HBM3 samples to Huawei, targeting mass production by end-2026 — though analysts widely see competitive HBM volume as a 2027–2028 prospect.
YMTC, China's NAND leader, is pushing into DRAM and HBM; a new Wuhan fab ramping in H2 2026 could make it the world's #3 NAND maker. Domestic tool-maker NAURA is building the equipment base behind both.
The read: China meaningfully relieves the commodity DRAM/NAND squeeze — for Chinese and non-U.S. devices, where HP, Dell, Acer and Asus qualify CXMT parts behind a compliance firewall. On HBM it sits ~two generations behind, constrained by U.S. equipment controls. Near-term risk to incumbents is margin compression on lower-end HBM3/3E after 2026 — not the HBM4 top end.
Volume advantage where it counts least for AI (commodity bits); a deep technology and equipment gap where it counts most (HBM). Counterpoint expects Korean firms to retain HBM dominance through the forecast window.
A live wire across the whole memory and storage stack — every story timestamped with when it was published, newest first. The feed auto-refreshes every 2 minutes; you can also pull manually. Filter by category, or switch between a continuous stream and a grouped-by-day view.
The offline fallback feed now starts with Jul 7–10 events: Samsung Q2 preliminary results, the Korean selloff, Micron’s >$250B plan, CXMT’s IPO schedule, SPHBM4 and SK hynix’s Nasdaq debut.
The honesty contract at work: every material error found during builds, disclosed rather than silently patched. Validation before every release has caught real bugs in nearly every session.
| Found | Where | What was wrong | Fix |
|---|---|---|---|
| Jun '26 | §06·F·B Backlogs | Microsoft 2023 shown as $112B — that was the cloud-only RPO subset, understating total commercial RPO by ~half | Corrected to ~$224B with SEC-anchored quarterly series |
| Jun '26 | §04·F Leveraged ETFs | MUU AUM shown ~$400M — a stale Nov-'25 snapshot; real figure ~$5.9B (~15× error) | Rebuilt all four funds on dense monthly data |
| Jun '26 | §04·E ETF Race | IBIT milestones mixed trading vs calendar days; axis too short for the ~$99B peak | Recomputed on calendar days; axis extended to 900d |
| Jun '26 | §06·H AWS Blocks | Jun-'25 ~45% cut wrongly implied to include Capacity Blocks — AWS explicitly excluded them (separate cut cadence, then hikes) | Two-track pricing rebuilt with dated anchors |
| Jun '26 | §04·D·S Short Interest | Garbled "debt cut $4.4B to $5.7B" figure in the FQ3 backdrop | Removed; replaced with clean sourced figures |
| Jun '26 | §06·F·B (code) | Duplicate const lg declaration — would have broken the entire dashboard's JS | Caught by pre-release validation; renamed |
| Jul '26 | §06·F·B Backlogs | Oracle's snapshot bar drew shorter than Microsoft's despite Oracle leading ($638B vs $627B) — segments summed to the May-vintage $553B | Hatched +$85B "post-snapshot" segment added |
| Jul '26 | build tooling | A Python \\n escaping bug injected three nav links into a JS string (join), breaking the whole file's script | Caught by validation before release; reversed byte-exact, re-applied correctly |
| Jul '26 | §04·D Targets | Rating-only firm entries added as pt:0 — the renderer draws proportional bars, so they would have shown $0-width bars | Caught in validation before release; entries removed, folded into prose |
| Jul '26 | freshness system | §04·B chip briefly set to a static date, misrepresenting a live-feed section | Self-caught same turn; reverted to 'live feed' |
| Jul '26 | §06·D·W per-MW | Table said GB300 ~4.1 PB/s while its own footnote math (490×8) gives 3.9; Rubin GPUs/MW 330 vs 340 | Harmonized before release; table and footnote now agree |
| Jul '26 | build wiring | Catalyst-calendar and provenance-index nav links + render hooks shipped without their sections — two dangling anchors (interrupted batch) | Sections built Jul 6; renderer verified against its DOM target |
The honesty contract in one view: this table is built at open, live, from every section’s own provenance footer — nothing here is written twice, so it cannot drift from the sections it indexes. Sections without a footer are visual/structural and say so.
The provenance index still builds from section footers at runtime. The new July freshness cards are additive and do not replace each section’s source/method footer.
Method. Assembled at runtime from each section’s final provenance footer (first ~170 characters, linked to the section). Structural sections without footers are listed as such rather than omitted. Not investment advice.